[RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies

Conor Dooley posted 5 patches 1 month, 3 weeks ago
There is a newer version of this series
[RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies
Posted by Conor Dooley 1 month, 3 weeks ago
From: Conor Dooley <conor.dooley@microchip.com>

Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 779f5cfab806e..abf2579171c5b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -605,6 +605,52 @@ properties:
           contains:
             const: zca
 
+      - if:
+          contains:
+            const: zve32x
+        then:
+          contains:
+            const: zicsr
+
+      - if:
+          contains:
+            const: zve32f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32x
+
+      - if:
+          contains:
+            const: zve64x
+        then:
+          contains:
+            const: zve32x
+
+      - if:
+          contains:
+            const: zve64f
+        then:
+          allOf:
+            - contains:
+                const: f
+            - contains:
+                const: zve32f
+            - contains:
+                const: zve64x
+
+      - if:
+          contains:
+            const: zve64d
+        then:
+          allOf:
+            - contains:
+                const: d
+            - contains:
+                const: zve64f
+
 allOf:
   # Zcf extension does not exist on rv64
   - if:
-- 
2.45.2
Re: [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies
Posted by Krzysztof Kozlowski 1 month, 3 weeks ago
On Wed, Oct 02, 2024 at 05:10:57PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
> in [1] says:
> | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
> | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension
> 
> | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
> | upon the F extension
> 
> | The Zve64d extension depends upon the D extension
> 
> Apply these rules to the bindings to help prevent invalid combinations.
> 
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof
Re: [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies
Posted by Clément Léger 1 month, 3 weeks ago

On 02/10/2024 18:10, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
> in [1] says:
> | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
> | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension
> 
> | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
> | upon the F extension
> 
> | The Zve64d extension depends upon the D extension
> 
> Apply these rules to the bindings to help prevent invalid combinations.
> 
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09 [1]
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 779f5cfab806e..abf2579171c5b 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -605,6 +605,52 @@ properties:
>            contains:
>              const: zca
>  
> +      - if:
> +          contains:
> +            const: zve32x
> +        then:
> +          contains:
> +            const: zicsr
> +
> +      - if:
> +          contains:
> +            const: zve32f
> +        then:
> +          allOf:
> +            - contains:
> +                const: f
> +            - contains:
> +                const: zve32x
> +
> +      - if:
> +          contains:
> +            const: zve64x
> +        then:
> +          contains:
> +            const: zve32x
> +
> +      - if:
> +          contains:
> +            const: zve64f
> +        then:
> +          allOf:
> +            - contains:
> +                const: f
> +            - contains:
> +                const: zve32f
> +            - contains:
> +                const: zve64x
> +
> +      - if:
> +          contains:
> +            const: zve64d
> +        then:
> +          allOf:
> +            - contains:
> +                const: d
> +            - contains:
> +                const: zve64f
> +
>  allOf:
>    # Zcf extension does not exist on rv64
>    - if:

Looks good to me.

Reviewed-by: Clément léger <cleger@rivosinc.com>

Thanks,

Clément