[PATCH V6 0/5] PCIe TPH and cache direct injection support

Wei Huang posted 5 patches 3 weeks, 5 days ago
Documentation/PCI/index.rst                   |   1 +
Documentation/PCI/tph.rst                     | 132 +++++
.../admin-guide/kernel-parameters.txt         |   4 +
Documentation/driver-api/pci/pci.rst          |   3 +
drivers/net/ethernet/broadcom/bnxt/bnxt.c     |  91 ++-
drivers/net/ethernet/broadcom/bnxt/bnxt.h     |   7 +
drivers/pci/Kconfig                           |  10 +
drivers/pci/Makefile                          |   1 +
drivers/pci/pci.c                             |   4 +
drivers/pci/pci.h                             |  12 +
drivers/pci/probe.c                           |   1 +
drivers/pci/tph.c                             | 544 ++++++++++++++++++
include/linux/pci-tph.h                       |  44 ++
include/linux/pci.h                           |   7 +
include/uapi/linux/pci_regs.h                 |  38 +-
net/core/netdev_rx_queue.c                    |   1 +
16 files changed, 890 insertions(+), 10 deletions(-)
create mode 100644 Documentation/PCI/tph.rst
create mode 100644 drivers/pci/tph.c
create mode 100644 include/linux/pci-tph.h
[PATCH V6 0/5] PCIe TPH and cache direct injection support
Posted by Wei Huang 3 weeks, 5 days ago
Hi All,

TPH (TLP Processing Hints) is a PCIe feature that allows endpoint
devices to provide optimization hints for requests that target memory
space. These hints, in a format called steering tag (ST), are provided
in the requester's TLP headers and allow the system hardware, including
the Root Complex, to optimize the utilization of platform resources
for the requests.

Upcoming AMD hardware implement a new Cache Injection feature that
leverages TPH. Cache Injection allows PCIe endpoints to inject I/O
Coherent DMA writes directly into an L2 within the CCX (core complex)
closest to the CPU core that will consume it. This technology is aimed
at applications requiring high performance and low latency, such as
networking and storage applications.

This series introduces generic TPH support in Linux, allowing STs to be
retrieved and used by PCIe endpoint drivers as needed. As a
demonstration, it includes an example usage in the Broadcom BNXT driver.
When running on Broadcom NICs with the appropriate firmware, it shows
substantial memory bandwidth savings and better network bandwidth using
real-world benchmarks. This solution is vendor-neutral and implemented
based on industry standards (PCIe Spec and PCI FW Spec).

V5->V6:
 * Rebase on top of pci/main (tag: pci-v6.12-changes)
 * Fix spellings and FIELD_PREP/bnxt.c compilation errors (Simon)
 * Move tph.c to drivers/pci directory (Lukas)
 * Remove CONFIG_ACPI dependency (Lukas)
 * Slightly re-arrange save/restore sequence (Lukas)

V4->V5:
 * Rebase on top of net-next/main tree (Broadcom)
 * Remove TPH mode query and TPH enabled checking functions (Bjorn)
 * Remove "nostmode" kernel parameter (Bjorn)
 * Add "notph" kernel parameter support (Bjorn)
 * Add back TPH documentation (Bjorn)
 * Change TPH register namings (Bjorn)
 * Squash TPH enable/disable/save/restore funcs as a single patch (Bjorn)
 * Squash ST get_st/set_st funcs as a single patch (Bjorn)
 * Replace nic_open/close with netdev_rx_queue_restart() (Jakub, Broadcom)

V3->V4:
 * Rebase on top of the latest pci/next tree (tag: 6.11-rc1)
 * Add new API functioins to query/enable/disable TPH support
 * Make pcie_tph_set_st() completely independent from pcie_tph_get_cpu_st()
 * Rewrite bnxt.c based on new APIs
 * Remove documentation for now due to constantly changing API
 * Remove pci=notph, but keep pci=nostmode with better flow (Bjorn)
 * Lots of code rewrite in tph.c & pci-tph.h with cleaner interface (Bjorn)
 * Add TPH save/restore support (Paul Luse and Lukas Wunner)

V2->V3:
 * Rebase on top of pci/next tree (tag: pci-v6.11-changes)
 * Redefine PCI TPH registers (pci_regs.h) without breaking uapi
 * Fix commit subjects/messages for kernel options (Jonathan and Bjorn)
 * Break API functions into three individual patches for easy review
 * Rewrite lots of code in tph.c/tph.h based (Jonathan and Bjorn)

V1->V2:
 * Rebase on top of pci.git/for-linus (6.10-rc1)
 * Address mismatched data types reported by Sparse (Sparse check passed)
 * Add pcie_tph_intr_vec_supported() for checking IRQ mode support
 * Skip bnxt affinity notifier registration if
   pcie_tph_intr_vec_supported()=false
 * Minor fixes in bnxt driver (i.e. warning messages)

Manoj Panicker (1):
  bnxt_en: Add TPH support in BNXT driver

Michael Chan (1):
  bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings

Wei Huang (3):
  PCI: Add TLP Processing Hints (TPH) support
  PCI/TPH: Add Steering Tag support
  PCI/TPH: Add TPH documentation

 Documentation/PCI/index.rst                   |   1 +
 Documentation/PCI/tph.rst                     | 132 +++++
 .../admin-guide/kernel-parameters.txt         |   4 +
 Documentation/driver-api/pci/pci.rst          |   3 +
 drivers/net/ethernet/broadcom/bnxt/bnxt.c     |  91 ++-
 drivers/net/ethernet/broadcom/bnxt/bnxt.h     |   7 +
 drivers/pci/Kconfig                           |  10 +
 drivers/pci/Makefile                          |   1 +
 drivers/pci/pci.c                             |   4 +
 drivers/pci/pci.h                             |  12 +
 drivers/pci/probe.c                           |   1 +
 drivers/pci/tph.c                             | 544 ++++++++++++++++++
 include/linux/pci-tph.h                       |  44 ++
 include/linux/pci.h                           |   7 +
 include/uapi/linux/pci_regs.h                 |  38 +-
 net/core/netdev_rx_queue.c                    |   1 +
 16 files changed, 890 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/PCI/tph.rst
 create mode 100644 drivers/pci/tph.c
 create mode 100644 include/linux/pci-tph.h

-- 
2.46.0
Re: [PATCH V6 0/5] PCIe TPH and cache direct injection support
Posted by Bjorn Helgaas 3 weeks, 2 days ago
On Fri, Sep 27, 2024 at 04:56:48PM -0500, Wei Huang wrote:
> Hi All,
> 
> TPH (TLP Processing Hints) is a PCIe feature that allows endpoint
> devices to provide optimization hints for requests that target memory
> space. These hints, in a format called steering tag (ST), are provided
> in the requester's TLP headers and allow the system hardware, including
> the Root Complex, to optimize the utilization of platform resources
> for the requests.
> 
> Upcoming AMD hardware implement a new Cache Injection feature that
> leverages TPH. Cache Injection allows PCIe endpoints to inject I/O
> Coherent DMA writes directly into an L2 within the CCX (core complex)
> closest to the CPU core that will consume it. This technology is aimed
> at applications requiring high performance and low latency, such as
> networking and storage applications.
> 
> This series introduces generic TPH support in Linux, allowing STs to be
> retrieved and used by PCIe endpoint drivers as needed. As a
> demonstration, it includes an example usage in the Broadcom BNXT driver.
> When running on Broadcom NICs with the appropriate firmware, it shows
> substantial memory bandwidth savings and better network bandwidth using
> real-world benchmarks. This solution is vendor-neutral and implemented
> based on industry standards (PCIe Spec and PCI FW Spec).
> 
> V5->V6:
>  * Rebase on top of pci/main (tag: pci-v6.12-changes)
>  * Fix spellings and FIELD_PREP/bnxt.c compilation errors (Simon)
>  * Move tph.c to drivers/pci directory (Lukas)
>  * Remove CONFIG_ACPI dependency (Lukas)
>  * Slightly re-arrange save/restore sequence (Lukas)

Thanks, I'll wait for the kernel test robot warnings to be resolved.

In patch 2/5, reword commit logs as imperative mood, e.g.,
s/X() is added/Add X()/, as you've already done for 1/5 and 3/5.

Maybe specify the ACPI _DSM name?  This would help users know whether
their system can use this, or help them request that a vendor
implement the _DSM.

In patch 4/5, s/sustancial/substantial/.  I guess the firmware you
refer to here means the system firmware that would provide the _DSM
required for this to work, i.e., not firmware on the NIC itself?
Would be helpful for users to have a hint as to how to tell whether to
expect a benefit on their system.

The 5/5 commit log could say what the patch *does*, not what *could*
be done (the subject does say what the patch does, but it's nice if
it's in the commit log as well so it's complete by itself).  Also, a
hint that using the steering tag helps direct DMA writes to a cache
close to the CPU expected to consume it might be helpful to motivate
the patch.

Bjorn
Re: [PATCH V6 0/5] PCIe TPH and cache direct injection support
Posted by Wei Huang 3 weeks ago

On 9/30/24 11:55, Bjorn Helgaas wrote:
> On Fri, Sep 27, 2024 at 04:56:48PM -0500, Wei Huang wrote:
>> Hi All,
>>
>> TPH (TLP Processing Hints) is a PCIe feature that allows endpoint
>> devices to provide optimization hints for requests that target memory
>> space. These hints, in a format called steering tag (ST), are provided
>> in the requester's TLP headers and allow the system hardware, including
>> the Root Complex, to optimize the utilization of platform resources
>> for the requests.
>>
>> Upcoming AMD hardware implement a new Cache Injection feature that
>> leverages TPH. Cache Injection allows PCIe endpoints to inject I/O
>> Coherent DMA writes directly into an L2 within the CCX (core complex)
>> closest to the CPU core that will consume it. This technology is aimed
>> at applications requiring high performance and low latency, such as
>> networking and storage applications.
>>
>> This series introduces generic TPH support in Linux, allowing STs to be
>> retrieved and used by PCIe endpoint drivers as needed. As a
>> demonstration, it includes an example usage in the Broadcom BNXT driver.
>> When running on Broadcom NICs with the appropriate firmware, it shows
>> substantial memory bandwidth savings and better network bandwidth using
>> real-world benchmarks. This solution is vendor-neutral and implemented
>> based on industry standards (PCIe Spec and PCI FW Spec).
>>
>> V5->V6:
>>  * Rebase on top of pci/main (tag: pci-v6.12-changes)
>>  * Fix spellings and FIELD_PREP/bnxt.c compilation errors (Simon)
>>  * Move tph.c to drivers/pci directory (Lukas)
>>  * Remove CONFIG_ACPI dependency (Lukas)
>>  * Slightly re-arrange save/restore sequence (Lukas)
> 
> Thanks, I'll wait for the kernel test robot warnings to be resolved.

Fixed in V7. I tested with clang 18.1.8 and compilation with W=1 passed.

> 
> In patch 2/5, reword commit logs as imperative mood, e.g.,
> s/X() is added/Add X()/, as you've already done for 1/5 and 3/5.

Fixed

> 
> Maybe specify the ACPI _DSM name?  This would help users know whether
> their system can use this, or help them request that a vendor
> implement the _DSM.

I added more information (rev, func, name) in the code and in the commit
message. End-users should be able to use this info to locate this _DSM
method in ACPI DSL.

> 
> In patch 4/5, s/sustancial/substantial/.  I guess the firmware you
> refer to here means the system firmware that would provide the _DSM
> required for this to work, i.e., not firmware on the NIC itself?
> Would be helpful for users to have a hint as to how to tell whether to
> expect a benefit on their system.

We need both NIC FW and system FW to support TPH. I revised the commit
message to clarify.

I cannot speak for Broadcom on which NIC FW version will support it. I
know that, upon release, this feature will be backward compatible and
carried on in the future.

> 
> The 5/5 commit log could say what the patch *does*, not what *could*
> be done (the subject does say what the patch does, but it's nice if
> it's in the commit log as well so it's complete by itself).  Also, a
> hint that using the steering tag helps direct DMA writes to a cache
> close to the CPU expected to consume it might be helpful to motivate
> the patch.

Fixed. Thanks you for the detailed feedback!

> 
> Bjorn