Add PLL locktime for PLL142XX controller.

Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Cc: stable@vger.kernel.org
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4be879ab917e..d4c5ae20de4f 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR	(270)
+#define PLL142XX_LOCK_FACTOR	(150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	if (pll->type == pll_142xx)
+		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+			pll->lock_reg);
+	else
+		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */
-- 
2.17.1

On 26/09/2024 16:45, Varada Pavani wrote:
> Add PLL locktime for PLL142XX controller.

You marked it as fixes. Please describe the observable bug and its
impact. See submitting patches and stable kernel rules.

> 
> Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> ---
Best regards,
Krzysztof

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: 30 September 2024 16:07
> To: Varada Pavani <v.pavani@samsung.com>; aswani.reddy@samsung.com;
> pankaj.dubey@samsung.com; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; alim.akhtar@samsung.com;
> mturquette@baylibre.com; sboyd@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: gost.dev@samsung.com; stable@vger.kernel.org
> Subject: Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used
> on FSD platfom
> 
> On 26/09/2024 16:45, Varada Pavani wrote:
> > Add PLL locktime for PLL142XX controller.
> 
> You marked it as fixes. Please describe the observable bug and its impact.
> See submitting patches and stable kernel rules.
> 

We marked it fixes because there is a software bug.  Both PLL142XX and
PLL35XX have same configurations with only change in locktime period
which is 150*PDIV . Hence updated locktime as per the defined spec.
Will update this information in the commit message and push V2 version.

Regards,
Varada Pavani

> >
> > Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> > ---
> Best regards,
> Krzysztof