Previously, CXL type3 devices (memory expanders) use hostonly
coherence (HDM-H), while CXL type2 devices (accelerators) use dev
coherence (HDM-D). So the target device type of a cxl decoder is
named as CXL_DECODER_HOSTONLYMEM for type3 devices and
CXL_DECODER_DEVMEM for type2 devices. However, this isn't true
anymore. CXL type3 devices can use dev coherence + back
invalidation (HDM-DB) too.
To avoid confusing between the device type and coherence, in this
patch, CXL_DECODER_HOSTONLYMEM/DEVMEM is renamed to
CXL_DECODER_EXPANDER/ACCEL.
No functionality change is expected in this patch.
Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>
---
drivers/cxl/acpi.c | 2 +-
drivers/cxl/core/hdm.c | 16 ++++++++--------
drivers/cxl/core/port.c | 6 +++---
drivers/cxl/core/region.c | 2 +-
drivers/cxl/cxl.h | 4 ++--
tools/testing/cxl/test/cxl.c | 6 +++---
6 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 3115f246273b..21486e471305 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -382,7 +382,7 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws,
cxld = &cxlrd->cxlsd.cxld;
cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->hpa_range = (struct range) {
.start = cfmws->base_hpa,
.end = cfmws->base_hpa + cfmws->window_size - 1,
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 3df10517a327..57b54ecdb000 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -572,7 +572,7 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl)
{
u32p_replace_bits(ctrl,
- !!(cxld->target_type == CXL_DECODER_HOSTONLYMEM),
+ !!(cxld->target_type == CXL_DECODER_EXPANDER),
CXL_HDM_DECODER0_CTRL_HOSTONLY);
}
@@ -771,7 +771,7 @@ static int cxl_setup_hdm_decoder_from_dvsec(
if (!len)
return -ENOENT;
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->commit = NULL;
cxld->reset = NULL;
cxld->hpa_range = info->dvsec_range[which];
@@ -847,9 +847,9 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)
cxld->flags |= CXL_DECODER_F_LOCK;
if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
else
- cxld->target_type = CXL_DECODER_DEVMEM;
+ cxld->target_type = CXL_DECODER_ACCEL;
guard(rwsem_write)(&cxl_region_rwsem);
if (cxld->id != cxl_num_decoders_committed(port)) {
@@ -876,16 +876,16 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
* more precision.
*/
if (cxlds->type == CXL_DEVTYPE_CLASSMEM)
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
else
- cxld->target_type = CXL_DECODER_DEVMEM;
+ cxld->target_type = CXL_DECODER_ACCEL;
} else {
/* To be overridden by region type at commit time */
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
}
if (!FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) &&
- cxld->target_type == CXL_DECODER_HOSTONLYMEM) {
+ cxld->target_type == CXL_DECODER_EXPANDER) {
ctrl |= CXL_HDM_DECODER0_CTRL_HOSTONLY;
writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
}
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 67a8dc4d7868..47ad6d9329db 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -135,9 +135,9 @@ static ssize_t target_type_show(struct device *dev,
struct cxl_decoder *cxld = to_cxl_decoder(dev);
switch (cxld->target_type) {
- case CXL_DECODER_DEVMEM:
+ case CXL_DECODER_ACCEL:
return sysfs_emit(buf, "accelerator\n");
- case CXL_DECODER_HOSTONLYMEM:
+ case CXL_DECODER_EXPANDER:
return sysfs_emit(buf, "expander\n");
}
return -ENXIO;
@@ -1768,7 +1768,7 @@ static int cxl_decoder_init(struct cxl_port *port, struct cxl_decoder *cxld)
/* Pre initialize an "empty" decoder */
cxld->interleave_ways = 1;
cxld->interleave_granularity = PAGE_SIZE;
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->hpa_range = (struct range) {
.start = 0,
.end = -1,
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 21ad5f242875..8229e8a0072d 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -2545,7 +2545,7 @@ static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd,
return ERR_PTR(-EBUSY);
}
- return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_HOSTONLYMEM);
+ return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_EXPANDER);
}
static ssize_t create_pmem_region_store(struct device *dev,
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 28c8783d3c14..55b8c32f8d72 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -324,8 +324,8 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
#define CXL_DECODER_F_MASK GENMASK(5, 0)
enum cxl_decoder_type {
- CXL_DECODER_DEVMEM = 2,
- CXL_DECODER_HOSTONLYMEM = 3,
+ CXL_DECODER_ACCEL = 2,
+ CXL_DECODER_EXPANDER = 3,
};
/*
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index 3982d292d286..352a62c745c6 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -724,7 +724,7 @@ static void default_mock_decoder(struct cxl_decoder *cxld)
cxld->interleave_ways = 1;
cxld->interleave_granularity = 256;
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->commit = mock_decoder_commit;
cxld->reset = mock_decoder_reset;
}
@@ -798,7 +798,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
cxld->interleave_ways = 2;
eig_to_granularity(window->granularity, &cxld->interleave_granularity);
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->flags = CXL_DECODER_F_ENABLE;
cxled->state = CXL_DECODER_STATE_AUTO;
port->commit_end = cxld->id;
@@ -831,7 +831,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
} else
cxlsd->target[0] = dport;
cxld = &cxlsd->cxld;
- cxld->target_type = CXL_DECODER_HOSTONLYMEM;
+ cxld->target_type = CXL_DECODER_EXPANDER;
cxld->flags = CXL_DECODER_F_ENABLE;
iter->commit_end = 0;
/*
--
2.39.2On Wed, Sep 25, 2024 at 10:46:44AM +0800, Huang Ying wrote: > Previously, CXL type3 devices (memory expanders) use hostonly > coherence (HDM-H), while CXL type2 devices (accelerators) use dev > coherence (HDM-D). So the target device type of a cxl decoder is > named as CXL_DECODER_HOSTONLYMEM for type3 devices and > CXL_DECODER_DEVMEM for type2 devices. However, this isn't true > anymore. CXL type3 devices can use dev coherence + back > invalidation (HDM-DB) too. > > To avoid confusing between the device type and coherence, in this > patch, CXL_DECODER_HOSTONLYMEM/DEVMEM is renamed to > CXL_DECODER_EXPANDER/ACCEL. > > No functionality change is expected in this patch. > > Signed-off-by: "Huang, Ying" <ying.huang@intel.com> > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Cc: Dan Williams <dan.j.williams@intel.com> > Cc: Davidlohr Bueso <dave@stgolabs.net> > Cc: Jonathan Cameron <jonathan.cameron@huawei.com> > Cc: Dave Jiang <dave.jiang@intel.com> > Cc: Alison Schofield <alison.schofield@intel.com> > Cc: Vishal Verma <vishal.l.verma@intel.com> > Cc: Ira Weiny <ira.weiny@intel.com> > Cc: Alejandro Lucero <alucerop@amd.com> > --- > drivers/cxl/acpi.c | 2 +- > drivers/cxl/core/hdm.c | 16 ++++++++-------- > drivers/cxl/core/port.c | 6 +++--- > drivers/cxl/core/region.c | 2 +- > drivers/cxl/cxl.h | 4 ++-- > tools/testing/cxl/test/cxl.c | 6 +++--- > 6 files changed, 18 insertions(+), 18 deletions(-) > Reviewed-by: Gregory Price <gourry@gourry.net>
On Wed, 25 Sep 2024, Huang Ying wrote: >Previously, CXL type3 devices (memory expanders) use hostonly >coherence (HDM-H), while CXL type2 devices (accelerators) use dev >coherence (HDM-D). So the target device type of a cxl decoder is >named as CXL_DECODER_HOSTONLYMEM for type3 devices and >CXL_DECODER_DEVMEM for type2 devices. However, this isn't true >anymore. CXL type3 devices can use dev coherence + back >invalidation (HDM-DB) too. > >To avoid confusing between the device type and coherence, in this >patch, CXL_DECODER_HOSTONLYMEM/DEVMEM is renamed to >CXL_DECODER_EXPANDER/ACCEL. > >No functionality change is expected in this patch. Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> >Signed-off-by: "Huang, Ying" <ying.huang@intel.com> >Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> >Cc: Dan Williams <dan.j.williams@intel.com> >Cc: Davidlohr Bueso <dave@stgolabs.net> >Cc: Jonathan Cameron <jonathan.cameron@huawei.com> >Cc: Dave Jiang <dave.jiang@intel.com> >Cc: Alison Schofield <alison.schofield@intel.com> >Cc: Vishal Verma <vishal.l.verma@intel.com> >Cc: Ira Weiny <ira.weiny@intel.com> >Cc: Alejandro Lucero <alucerop@amd.com>
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