Add the definition for the X86_FEATURE_INVLPGB CPUID flag.

Tested by booting a kernel with this change on an AMD Milan system,
and making sure the "invlpgb" flag shows up in /proc/cpuinfo

Signed-off-by: Rik van Riel <riel@surriel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index dd4682857c12..9a98cc7ded39 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -335,6 +335,7 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* "irperf" Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
+#define X86_FEATURE_INVLPGB		(13*32+ 3) /* "invlpgb" INVLPGB instruction */
 #define X86_FEATURE_RDPRU		(13*32+ 4) /* "rdpru" Read processor register at user level */
 #define X86_FEATURE_WBNOINVD		(13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */
-- 
2.45.2

On September 24, 2024 11:00:13 PM GMT+01:00, Rik van Riel <riel@surriel.com> wrote:
>Add the definition for the X86_FEATURE_INVLPGB CPUID flag.
>
>Tested by booting a kernel with this change on an AMD Milan system,
>and making sure the "invlpgb" flag shows up in /proc/cpuinfo

Why?

-- 
Sent from a small device: formatting sucks and brevity is inevitable.

On Wed, 2024-09-25 at 08:45 +0100, Borislav Petkov wrote:
> On September 24, 2024 11:00:13 PM GMT+01:00, Rik van Riel
> <riel@surriel.com> wrote:
> > Add the definition for the X86_FEATURE_INVLPGB CPUID flag.
> > 
> > Tested by booting a kernel with this change on an AMD Milan system,
> > and making sure the "invlpgb" flag shows up in /proc/cpuinfo
> 
> Why?
> 

I would like to avoid TLB flush IPIs for the top N (maybe 8 or 16?)
TLB flushing processes in the system.  We can figure out what these
processes are by keeping a score of TLB flushes * number of CPUs over
some time period.

That seems like something AMD CPUs might be able to do, without
running out of PCIDs even on larger systems.

The TLB flush IPIs are taking a considerable amount of compute
power across a large fleet, and is something I would like to
optimize.

-- 
All Rights Reversed.

On Wed, Sep 25, 2024 at 12:46:39PM -0400, Rik van Riel wrote:
> I would like to avoid TLB flush IPIs for the top N (maybe 8 or 16?)
> TLB flushing processes in the system.  We can figure out what these
> processes are by keeping a score of TLB flushes * number of CPUs over
> some time period.

Documentation/arch/x86/cpuinfo.rst

What does that have to do with showing the flag in /proc/cpuinfo?

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

On 9/24/2024 3:00 PM, Rik van Riel wrote:
> Add the definition for the X86_FEATURE_INVLPGB CPUID flag.
> 
> Tested by booting a kernel with this change on an AMD Milan system,
> and making sure the "invlpgb" flag shows up in /proc/cpuinfo
> 
> Signed-off-by: Rik van Riel <riel@surriel.com>

Now there is a need to also update the CPUID database:

https://lore.kernel.org/lkml/87o7642u7w.ffs@tglx/

Thanks!
     Xin

> ---
>   arch/x86/include/asm/cpufeatures.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index dd4682857c12..9a98cc7ded39 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -335,6 +335,7 @@
>   #define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */
>   #define X86_FEATURE_IRPERF		(13*32+ 1) /* "irperf" Instructions Retired Count */
>   #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
> +#define X86_FEATURE_INVLPGB		(13*32+ 3) /* "invlpgb" INVLPGB instruction */
>   #define X86_FEATURE_RDPRU		(13*32+ 4) /* "rdpru" Read processor register at user level */
>   #define X86_FEATURE_WBNOINVD		(13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
>   #define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */

On Tue, 2024-09-24 at 20:33 -0700, Xin Li wrote:
> On 9/24/2024 3:00 PM, Rik van Riel wrote:
> > Add the definition for the X86_FEATURE_INVLPGB CPUID flag.
> > 
> > Tested by booting a kernel with this change on an AMD Milan system,
> > and making sure the "invlpgb" flag shows up in /proc/cpuinfo
> > 
> > Signed-off-by: Rik van Riel <riel@surriel.com>
> 
> Now there is a need to also update the CPUID database:
> 
> https://lore.kernel.org/lkml/87o7642u7w.ffs@tglx/

The invlpgb flag is already in the CPUID database:

https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/tip/db/xml/leaf_80000008.xml#L53

-- 
All Rights Reversed.