Define the sdr104-specific offsets, preventing the driver from
defaulting to the 1.8V offsets, which cause the system to hang during
the SDR104 mode calibration.

The zeroing of these values was chosen since it restores functionality
and no better suggestions are provided by the Tegra X1 TRM.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 882b1d1f4ada8d9e275e5a6bee633a21cc6cdb2d..942e3a0f81ed768021d2ac25f6369998a9fbfd76 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1218,6 +1218,8 @@ mmc@700b0000 {
 		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
 		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
 		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>;
+		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>;
 		nvidia,default-tap = <0x2>;
 		nvidia,default-trim = <0x4>;
 		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,

---
base-commit: de5cb0dcb74c294ec527eddfe5094acfdb21ff21
change-id: 20240923-sdr104-36cca57a9049

Best regards,
-- 
Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>

From: Thierry Reding <treding@nvidia.com>


On Mon, 23 Sep 2024 19:24:51 +0100, Diogo Ivo wrote:
> Define the sdr104-specific offsets, preventing the driver from
> defaulting to the 1.8V offsets, which cause the system to hang during
> the SDR104 mode calibration.
> 
> The zeroing of these values was chosen since it restores functionality
> and no better suggestions are provided by the Tegra X1 TRM.
> 
> [...]

Applied, thanks!

[1/1] arm64: tegra: Add SDMMC sdr104-offsets for Tegra X1
      commit: 87b90082179daf87969ad9ff44032acc59d9086a

Best regards,
-- 
Thierry Reding <treding@nvidia.com>

Hello,

Gentle ping on this patch.

Best regards,
Diogo

On Mon Sep 23, 2024 at 7:24 PM WEST, Diogo Ivo wrote:
> Define the sdr104-specific offsets, preventing the driver from
> defaulting to the 1.8V offsets, which cause the system to hang during
> the SDR104 mode calibration.
>
> The zeroing of these values was chosen since it restores functionality
> and no better suggestions are provided by the Tegra X1 TRM.
>
> Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>