Add the global clock controller support for QCS615 SoC.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 3045 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index a3e2a09e2105..52a7ba6d4cbf 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -467,6 +467,15 @@ config QCS_GCC_404
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
+config QCS_GCC_615
+ tristate "QCS615 Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select QCOM_GDSC
+ help
+ Support for the global clock controller on QCS615 devices.
+ Say Y if you want to use multimedia devices or peripheral
+ devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
+
config SC_CAMCC_7180
tristate "SC7180 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 2b378667a63f..a46ce0723602 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
+obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
new file mode 100644
index 000000000000..7db55a5d8e80
--- /dev/null
+++ b/drivers/clk/qcom/gcc-qcs615.c
@@ -0,0 +1,3035 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,qcs615-gcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_BI_TCXO_AO,
+ DT_SLEEP_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_GPLL0_OUT_AUX2_DIV,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL3_OUT_MAIN,
+ P_GPLL3_OUT_MAIN_DIV,
+ P_GPLL4_OUT_MAIN,
+ P_GPLL6_OUT_MAIN,
+ P_GPLL7_OUT_MAIN,
+ P_GPLL8_OUT_MAIN,
+ P_SLEEP_CLK,
+};
+
+static struct clk_alpha_pll gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_out_aux2_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll0_out_aux2_div",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll3 = {
+ .offset = 0x3000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll3",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll3_out_aux2_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "gpll3_out_aux2_div",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &gpll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4 = {
+ .offset = 0x76000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll4",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll6 = {
+ .offset = 0x13000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll6",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gpll6_out_main[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv gpll6_out_main = {
+ .offset = 0x13000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_gpll6_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll6_out_main",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll6.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll7 = {
+ .offset = 0x1a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll7",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll8 = {
+ .offset = 0x1b000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gpll8",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gpll8_out_main[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv gpll8_out_main = {
+ .offset = 0x1b000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_gpll8_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpll8_out_main",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll8.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct clk_parent_data gcc_parent_data_0_ao[] = {
+ { .index = DT_BI_TCXO_AO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL6_OUT_MAIN, 2 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll6_out_main.clkr.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL7_OUT_MAIN, 3 },
+ { P_GPLL4_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll7.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL7_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll7.clkr.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL3_OUT_MAIN_DIV, 4 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_7[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll3_out_aux2_div.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_8[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL8_OUT_MAIN, 2 },
+ { P_GPLL4_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_AUX2_DIV, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_8[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll8_out_main.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0_out_aux2_div.hw },
+};
+
+static const struct parent_map gcc_parent_map_9[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL3_OUT_MAIN, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_9[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll3.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
+ .cmd_rcgr = 0x48014,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cpuss_ahb_clk_src",
+ .parent_data = gcc_parent_data_0_ao,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
+ F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
+ F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_emac_ptp_clk_src = {
+ .cmd_rcgr = 0x6038,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_5,
+ .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_ptp_clk_src",
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
+ F(2500000, P_BI_TCXO, 1, 25, 192),
+ F(5000000, P_BI_TCXO, 1, 25, 96),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
+ F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
+ F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
+ .cmd_rcgr = 0x601c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_6,
+ .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_rgmii_clk_src",
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+ F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp1_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp2_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp3_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
+ .cmd_rcgr = 0x6b02c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
+ .cmd_rcgr = 0x6f014,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_phy_refgen_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
+ F(60000000, P_GPLL0_OUT_AUX2_DIV, 5, 0, 0),
+ F(133250000, P_GPLL3_OUT_MAIN_DIV, 4, 0, 0),
+ F(266500000, P_GPLL3_OUT_MAIN_DIV, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qspi_core_clk_src = {
+ .cmd_rcgr = 0x4b008,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_7,
+ .freq_tbl = ftbl_gcc_qspi_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qspi_core_clk_src",
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, P_GPLL0_OUT_AUX2_DIV, 1, 384, 15625),
+ F(14745600, P_GPLL0_OUT_AUX2_DIV, 1, 768, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_GPLL0_OUT_AUX2_DIV, 1, 1536, 15625),
+ F(32000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 75),
+ F(48000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 25),
+ F(64000000, P_GPLL0_OUT_AUX2_DIV, 1, 16, 75),
+ F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
+ F(80000000, P_GPLL0_OUT_AUX2_DIV, 1, 4, 15),
+ F(96000000, P_GPLL0_OUT_AUX2_DIV, 1, 8, 25),
+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(102400000, P_GPLL0_OUT_AUX2_DIV, 1, 128, 375),
+ F(112000000, P_GPLL0_OUT_AUX2_DIV, 1, 28, 75),
+ F(117964800, P_GPLL0_OUT_AUX2_DIV, 1, 6144, 15625),
+ F(120000000, P_GPLL0_OUT_AUX2_DIV, 2.5, 0, 0),
+ F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s0_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+ .cmd_rcgr = 0x17148,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s1_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+ .cmd_rcgr = 0x17278,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s2_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+ .cmd_rcgr = 0x173a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s3_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+ .cmd_rcgr = 0x174d8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s4_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+ .cmd_rcgr = 0x17608,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s5_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+ .cmd_rcgr = 0x17738,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s0_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+ .cmd_rcgr = 0x18148,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s1_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+ .cmd_rcgr = 0x18278,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s2_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+ .cmd_rcgr = 0x183a8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s3_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+ .cmd_rcgr = 0x184d8,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s4_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+ .cmd_rcgr = 0x18608,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s5_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+ .cmd_rcgr = 0x18738,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+ F(144000, P_BI_TCXO, 16, 3, 25),
+ F(400000, P_BI_TCXO, 12, 1, 4),
+ F(20000000, P_GPLL0_OUT_AUX2_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_OUT_AUX2_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
+ F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
+ F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x12028,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x12010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ice_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(400000, P_BI_TCXO, 12, 1, 4),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_AUX2_DIV, 3, 0, 0),
+ F(202000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x1400c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc2_apps_clk_src",
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .ops = &clk_rcg2_floor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+ F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
+ F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
+ .cmd_rcgr = 0x77020,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_axi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+ F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
+ .cmd_rcgr = 0x77048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_ice_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
+ .cmd_rcgr = 0x7707c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_OUT_AUX2_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
+ .cmd_rcgr = 0x77060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_unipro_core_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb20_sec_master_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+ F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb20_sec_master_clk_src = {
+ .cmd_rcgr = 0xa601c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb20_sec_master_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb20_sec_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb20_sec_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xa6034,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb20_sec_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb2_sec_phy_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb2_sec_phy_aux_clk_src = {
+ .cmd_rcgr = 0xa6060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_sec_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, P_GPLL0_OUT_AUX2_DIV, 4.5, 0, 0),
+ F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+ .cmd_rcgr = 0xf01c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(20000000, P_GPLL0_OUT_AUX2_DIV, 15, 0, 0),
+ F(40000000, P_GPLL0_OUT_AUX2_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf034,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+ .cmd_rcgr = 0xf060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_usb2_sec_phy_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_prim_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_vsensor_clk_src = {
+ .cmd_rcgr = 0x7a018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_9,
+ .freq_tbl = ftbl_gcc_vsensor_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_vsensor_clk_src",
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
+ .halt_reg = 0x770c0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x770c0,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x770c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_aggre_ufs_phy_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre_usb2_sec_axi_clk = {
+ .halt_reg = 0xa6084,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xa6084,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_aggre_usb2_sec_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb20_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
+ .halt_reg = 0xf07c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xf07c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_aggre_usb3_prim_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ahb2phy_east_clk = {
+ .halt_reg = 0x6a008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6a008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x6a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ahb2phy_east_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ahb2phy_west_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6a004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ahb2phy_west_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x38004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_camera_hf_axi_clk = {
+ .halt_reg = 0xb030,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_camera_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_ahb_clk = {
+ .halt_reg = 0x4100c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4100c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ce1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_axi_clk = {
+ .halt_reg = 0x41008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ce1_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce1_clk = {
+ .halt_reg = 0x41004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ce1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_sec_axi_clk = {
+ .halt_reg = 0xa609c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xa609c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cfg_noc_usb2_sec_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb20_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+ .halt_reg = 0xf078,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xf078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cpuss_ahb_clk = {
+ .halt_reg = 0x48000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(21),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_cpuss_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_cpuss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
+ .halt_reg = 0x71154,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x71154,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ddrss_gpu_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_disp_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll0_out_aux2_div.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_disp_hf_axi_clk = {
+ .halt_reg = 0xb038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_disp_hf_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_emac_axi_clk = {
+ .halt_reg = 0x6010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_emac_ptp_clk = {
+ .halt_reg = 0x6034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_ptp_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_emac_ptp_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_emac_rgmii_clk = {
+ .halt_reg = 0x6018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_rgmii_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_emac_rgmii_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_emac_slv_ahb_clk = {
+ .halt_reg = 0x6014,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x6014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x6014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_emac_slv_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gp3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_gp3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpu_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(16),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpu_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll0_out_aux2_div.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_iref_clk = {
+ .halt_reg = 0x8c010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpu_iref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
+ .halt_reg = 0x7100c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x7100c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpu_memnoc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+ .halt_reg = 0x71018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x71018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_gpu_snoc_dvm_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_phy_refgen_clk = {
+ .halt_reg = 0x6f02c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6f02c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_phy_refgen_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_phy_refgen_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+ .halt_reg = 0x6b020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+ .halt_reg = 0x6b01c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6b01c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_clkref_clk = {
+ .halt_reg = 0x8c00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+ .halt_reg = 0x6b018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+ .halt_reg = 0x6b024,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+ .halt_reg = 0x6b014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6b014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
+ .halt_reg = 0x6b010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_0_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+ .halt_reg = 0x6f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pcie_0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_pdm2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x33004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+ .halt_reg = 0x33008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pdm_xo4_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x34004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
+ .halt_reg = 0xb018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xb018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qmip_camera_nrt_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_disp_ahb_clk = {
+ .halt_reg = 0xb020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xb020,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qmip_disp_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_pcie_ahb_clk = {
+ .halt_reg = 0x6b044,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6b044,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(28),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qmip_pcie_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
+ .halt_reg = 0xb014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0xb014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0xb014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qmip_video_vcodec_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
+ .halt_reg = 0x4b000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x4b000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qspi_cnoc_periph_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_core_clk = {
+ .halt_reg = 0x4b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qspi_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qspi_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
+ .halt_reg = 0x17014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(9),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_clk = {
+ .halt_reg = 0x1700c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
+ .halt_reg = 0x17144,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
+ .halt_reg = 0x17274,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(11),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
+ .halt_reg = 0x173a4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
+ .halt_reg = 0x174d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
+ .halt_reg = 0x17604,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
+ .halt_reg = 0x17734,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap0_s5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
+ .halt_reg = 0x18014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(18),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_clk = {
+ .halt_reg = 0x1800c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
+ .halt_reg = 0x18144,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
+ .halt_reg = 0x18274,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s1_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
+ .halt_reg = 0x183a4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s2_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
+ .halt_reg = 0x184d4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s3_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
+ .halt_reg = 0x18604,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s4_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
+ .halt_reg = 0x18734,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(27),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap1_s5_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_0_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
+ .halt_reg = 0x17008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x17008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_0_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
+ .halt_reg = 0x18004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_1_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
+ .halt_reg = 0x18008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x18008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(21),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qupv3_wrap_1_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x8c030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx3_usb2_clkref_clk = {
+ .halt_reg = 0x8c038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x8c038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_rx3_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x12008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x12004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sdcc1_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_sdcc2_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
+ .halt_reg = 0x4819c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_sys_noc_cpuss_ahb_clk",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_card_clkref_clk = {
+ .halt_reg = 0x8c004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x8c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_card_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_mem_clkref_clk = {
+ .halt_reg = 0x8c000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8c000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_mem_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_ahb_clk = {
+ .halt_reg = 0x77014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x77014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_axi_clk = {
+ .halt_reg = 0x77010,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77010,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_axi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_ufs_phy_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
+ .halt_reg = 0x77044,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77044,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_ice_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
+ .halt_reg = 0x77078,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77078,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
+ .halt_reg = 0x7701c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x7701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
+ .halt_reg = 0x77018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x77018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
+ .halt_reg = 0x77040,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x77040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_ufs_phy_unipro_core_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sec_master_clk = {
+ .halt_reg = 0xa6010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xa6010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb20_sec_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb20_sec_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sec_mock_utmi_clk = {
+ .halt_reg = 0xa6018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa6018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb20_sec_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb20_sec_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sec_sleep_clk = {
+ .halt_reg = 0xa6014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa6014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb20_sec_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_prim_clkref_clk = {
+ .halt_reg = 0x8c028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x8c028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_prim_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_sec_clkref_clk = {
+ .halt_reg = 0x8c018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x8c018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_sec_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_sec_phy_aux_clk = {
+ .halt_reg = 0xa6050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa6050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_sec_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb2_sec_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_sec_phy_com_aux_clk = {
+ .halt_reg = 0xa6054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa6054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_sec_phy_com_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb2_sec_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_sec_phy_pipe_clk = {
+ .halt_reg = 0xa6058,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0xa6058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb2_sec_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_master_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_master_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
+ .halt_reg = 0xf018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_sleep_clk = {
+ .halt_reg = 0xf014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_clkref_clk = {
+ .halt_reg = 0x8c014,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8c014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_prim_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
+ .halt_reg = 0xf050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_prim_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
+ .halt_reg = 0xf054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_prim_phy_com_aux_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
+ .halt_reg = 0xf058,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0xf058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_prim_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_sec_clkref_clk = {
+ .halt_reg = 0x8c008,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x8c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb3_sec_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+
+static struct clk_branch gcc_video_axi0_clk = {
+ .halt_reg = 0xb024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_video_axi0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *gcc_qcs615_hws[] = {
+ [GPLL0_OUT_AUX2_DIV] = &gpll0_out_aux2_div.hw,
+ [GPLL3_OUT_AUX2_DIV] = &gpll3_out_aux2_div.hw,
+};
+
+static struct gdsc emac_gdsc = {
+ .gdscr = 0x6004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "emac_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ufs_phy_gdsc = {
+ .gdscr = 0x77004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "ufs_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb20_sec_gdsc = {
+ .gdscr = 0xa6004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "usb20_sec_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc usb30_prim_gdsc = {
+ .gdscr = 0xf004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
+ .pd = {
+ .name = "usb30_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
+ .gdscr = 0x7d040,
+ .pd = {
+ .name = "hlos1_vote_aggre_noc_mmu_audio_tbu",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
+ .gdscr = 0x7d044,
+ .pd = {
+ .name = "hlos1_vote_aggre_noc_mmu_tbu1",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
+ .gdscr = 0x7d048,
+ .pd = {
+ .name = "hlos1_vote_aggre_noc_mmu_tbu2",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
+ .gdscr = 0x7d04c,
+ .pd = {
+ .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
+ .gdscr = 0x7d050,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
+ .gdscr = 0x7d054,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
+ .gdscr = 0x7d058,
+ .pd = {
+ .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct clk_regmap *gcc_qcs615_clocks[] = {
+ [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
+ [GCC_AGGRE_USB2_SEC_AXI_CLK] = &gcc_aggre_usb2_sec_axi_clk.clkr,
+ [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
+ [GCC_AHB2PHY_EAST_CLK] = &gcc_ahb2phy_east_clk.clkr,
+ [GCC_AHB2PHY_WEST_CLK] = &gcc_ahb2phy_west_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
+ [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
+ [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
+ [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
+ [GCC_CFG_NOC_USB2_SEC_AXI_CLK] = &gcc_cfg_noc_usb2_sec_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
+ [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
+ [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
+ [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
+ [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
+ [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
+ [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
+ [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
+ [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
+ [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
+ [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
+ [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
+ [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
+ [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
+ [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
+ [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+ [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
+ [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+ [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
+ [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+ [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
+ [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+ [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+ [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+ [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
+ [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+ [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
+ [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
+ [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
+ [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
+ [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
+ [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
+ [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_RX3_USB2_CLKREF_CLK] = &gcc_rx3_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
+ [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
+ [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
+ [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
+ [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
+ [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
+ [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
+ [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
+ [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
+ [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
+ [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
+ [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
+ [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
+ [GCC_USB20_SEC_MASTER_CLK] = &gcc_usb20_sec_master_clk.clkr,
+ [GCC_USB20_SEC_MASTER_CLK_SRC] = &gcc_usb20_sec_master_clk_src.clkr,
+ [GCC_USB20_SEC_MOCK_UTMI_CLK] = &gcc_usb20_sec_mock_utmi_clk.clkr,
+ [GCC_USB20_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb20_sec_mock_utmi_clk_src.clkr,
+ [GCC_USB20_SEC_SLEEP_CLK] = &gcc_usb20_sec_sleep_clk.clkr,
+ [GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr,
+ [GCC_USB2_SEC_CLKREF_CLK] = &gcc_usb2_sec_clkref_clk.clkr,
+ [GCC_USB2_SEC_PHY_AUX_CLK] = &gcc_usb2_sec_phy_aux_clk.clkr,
+ [GCC_USB2_SEC_PHY_AUX_CLK_SRC] = &gcc_usb2_sec_phy_aux_clk_src.clkr,
+ [GCC_USB2_SEC_PHY_COM_AUX_CLK] = &gcc_usb2_sec_phy_com_aux_clk.clkr,
+ [GCC_USB2_SEC_PHY_PIPE_CLK] = &gcc_usb2_sec_phy_pipe_clk.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
+ [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
+ [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
+ [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
+ [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
+ [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
+ [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL3] = &gpll3.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [GPLL6] = &gpll6.clkr,
+ [GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
+ [GPLL7] = &gpll7.clkr,
+ [GPLL8] = &gpll8.clkr,
+ [GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
+};
+
+static struct gdsc *gcc_qcs615_gdscs[] = {
+ [EMAC_GDSC] = &emac_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+ [UFS_PHY_GDSC] = &ufs_phy_gdsc,
+ [USB20_SEC_GDSC] = &usb20_sec_gdsc,
+ [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
+ [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
+ [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
+};
+
+static const struct qcom_reset_map gcc_qcs615_resets[] = {
+ [GCC_EMAC_BCR] = { 0x6000 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0xd000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0xd004 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB2_PHY_SEC_BCR] = { 0x50018 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
+ [GCC_PCIE_0_BCR] = { 0x6b000 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+ [GCC_PCIE_PHY_BCR] = { 0x6f000 },
+ [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB20_SEC_BCR] = { 0xa6000 },
+ [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x50008 },
+ [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
+ [GCC_SDCC1_BCR] = { 0x12000 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+};
+
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+};
+
+static const struct regmap_config gcc_qcs615_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xa609c,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_qcs615_desc = {
+ .config = &gcc_qcs615_regmap_config,
+ .clk_hws = gcc_qcs615_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_qcs615_hws),
+ .clks = gcc_qcs615_clocks,
+ .num_clks = ARRAY_SIZE(gcc_qcs615_clocks),
+ .resets = gcc_qcs615_resets,
+ .num_resets = ARRAY_SIZE(gcc_qcs615_resets),
+ .gdscs = gcc_qcs615_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
+};
+
+static const struct of_device_id gcc_qcs615_match_table[] = {
+ { .compatible = "qcom,qcs615-gcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_qcs615_match_table);
+
+static int gcc_qcs615_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &gcc_qcs615_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+ /*
+ * Disable the GPLL0 active input to MM blocks and GPU
+ * via MISC registers.
+ */
+ regmap_update_bits(regmap, 0x0b084, BIT(0), BIT(0));
+ regmap_update_bits(regmap, 0x9b000, BIT(0), BIT(0));
+
+ /* Keep some clocks always enabled */
+ qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */
+ qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */
+ qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */
+ qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */
+ qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
+ qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */
+ qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */
+ qcom_branch_set_clk_en(regmap, 0x480040); /* GCC_CPUSS_GNOC_CLK */
+
+ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+ ARRAY_SIZE(gcc_dfs_clocks));
+ if (ret)
+ return ret;
+
+
+ return qcom_cc_really_probe(&pdev->dev, &gcc_qcs615_desc, regmap);
+}
+
+static struct platform_driver gcc_qcs615_driver = {
+ .probe = gcc_qcs615_probe,
+ .driver = {
+ .name = "gcc-qcs615",
+ .of_match_table = gcc_qcs615_match_table,
+ },
+};
+
+static int __init gcc_qcs615_init(void)
+{
+ return platform_driver_register(&gcc_qcs615_driver);
+}
+subsys_initcall(gcc_qcs615_init);
+
+static void __exit gcc_qcs615_exit(void)
+{
+ platform_driver_unregister(&gcc_qcs615_driver);
+}
+module_exit(gcc_qcs615_exit);
+
+MODULE_DESCRIPTION("QTI GCC QCS615 Driver");
+MODULE_LICENSE("GPL");
--
2.45.2On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
> Add the global clock controller support for QCS615 SoC.
>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 3045 insertions(+)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index a3e2a09e2105..52a7ba6d4cbf 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -467,6 +467,15 @@ config QCS_GCC_404
> Say Y if you want to use multimedia devices or peripheral
> devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
>
> +config QCS_GCC_615
> + tristate "QCS615 Global Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + select QCOM_GDSC
> + help
> + Support for the global clock controller on QCS615 devices.
> + Say Y if you want to use multimedia devices or peripheral
> + devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
> +
> config SC_CAMCC_7180
> tristate "SC7180 Camera Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 2b378667a63f..a46ce0723602 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -70,6 +70,7 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
> obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
> obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
> +obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
> obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
> obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
> obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
> diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
> new file mode 100644
> index 000000000000..7db55a5d8e80
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-qcs615.c
> @@ -0,0 +1,3035 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + DT_BI_TCXO,
> + DT_BI_TCXO_AO,
> + DT_SLEEP_CLK,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_GPLL0_OUT_AUX2_DIV,
> + P_GPLL0_OUT_MAIN,
> + P_GPLL3_OUT_MAIN,
> + P_GPLL3_OUT_MAIN_DIV,
> + P_GPLL4_OUT_MAIN,
> + P_GPLL6_OUT_MAIN,
> + P_GPLL7_OUT_MAIN,
> + P_GPLL8_OUT_MAIN,
> + P_SLEEP_CLK,
> +};
> +
> +static struct clk_alpha_pll gpll0 = {
> + .offset = 0x0,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll0",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll0_out_aux2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll0_out_aux2_div",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
Should it be clk_alpha_pll_postdiv_foo_ops ?
> +
> +static struct clk_alpha_pll gpll3 = {
> + .offset = 0x3000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(3),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll3",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll3_out_aux2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data) {
> + .name = "gpll3_out_aux2_div",
> + .parent_data = &(const struct clk_parent_data) {
> + .hw = &gpll3.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
Should it be clk_alpha_pll_postdiv_foo_ops ?
> +
> +static struct clk_alpha_pll gpll4 = {
> + .offset = 0x76000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(4),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll4",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll gpll6 = {
> + .offset = 0x13000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(6),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll6",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static const struct clk_div_table post_div_table_gpll6_out_main[] = {
> + { 0x1, 2 },
> + { }
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll6_out_main = {
> + .offset = 0x13000,
> + .post_div_shift = 8,
> + .post_div_table = post_div_table_gpll6_out_main,
> + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
> + .width = 4,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gpll6_out_main",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gpll6.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll7 = {
> + .offset = 0x1a000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(7),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll7",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll gpll8 = {
> + .offset = 0x1b000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(8),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gpll8",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static const struct clk_div_table post_div_table_gpll8_out_main[] = {
> + { 0x1, 2 },
> + { }
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll8_out_main = {
> + .offset = 0x1b000,
> + .post_div_shift = 8,
> + .post_div_table = post_div_table_gpll8_out_main,
> + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
> + .width = 4,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gpll8_out_main",
> + .parent_hws = (const struct clk_hw*[]) {
> + &gpll8.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static const struct parent_map gcc_parent_map_0[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_0[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_0_ao[] = {
> + { .index = DT_BI_TCXO_AO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_1[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL6_OUT_MAIN, 2 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll6_out_main.clkr.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_2[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_SLEEP_CLK, 5 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_2[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .index = DT_SLEEP_CLK },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_3[] = {
> + { P_BI_TCXO, 0 },
> + { P_SLEEP_CLK, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_3[] = {
> + { .index = DT_BI_TCXO },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_4[] = {
> + { P_BI_TCXO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_4[] = {
> + { .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_5[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL7_OUT_MAIN, 3 },
> + { P_GPLL4_OUT_MAIN, 5 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_5[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll7.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_6[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL7_OUT_MAIN, 3 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_6[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll7.clkr.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_7[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL3_OUT_MAIN_DIV, 4 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_7[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll3_out_aux2_div.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_8[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL8_OUT_MAIN, 2 },
> + { P_GPLL4_OUT_MAIN, 5 },
> + { P_GPLL0_OUT_AUX2_DIV, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_8[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll8_out_main.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0_out_aux2_div.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_9[] = {
> + { P_BI_TCXO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL3_OUT_MAIN, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_9[] = {
> + { .index = DT_BI_TCXO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll3.clkr.hw },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
> + .cmd_rcgr = 0x48014,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_cpuss_ahb_clk_src",
> + .parent_data = gcc_parent_data_0_ao,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_emac_ptp_clk_src = {
> + .cmd_rcgr = 0x6038,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_5,
> + .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_emac_ptp_clk_src",
> + .parent_data = gcc_parent_data_5,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
> + F(2500000, P_BI_TCXO, 1, 25, 192),
> + F(5000000, P_BI_TCXO, 1, 25, 96),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
> + .cmd_rcgr = 0x601c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_6,
> + .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_emac_rgmii_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_gp1_clk_src = {
> + .cmd_rcgr = 0x64004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_gp1_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_gp2_clk_src = {
> + .cmd_rcgr = 0x65004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_gp2_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_gp3_clk_src = {
> + .cmd_rcgr = 0x66004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_gp3_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
> + F(9600000, P_BI_TCXO, 2, 0, 0),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
> + .cmd_rcgr = 0x6b02c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_3,
> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_pcie_0_aux_clk_src",
> + .parent_data = gcc_parent_data_3,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> + .ops = &clk_rcg2_ops,
Should it be using shared ops?
I think there are other clocks here which are usually
clk_rcg2_shared_ops.
> + },
> +};
> +
[...]
> +static struct clk_rcg2 gcc_vsensor_clk_src = {
> + .cmd_rcgr = 0x7a018,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_9,
> + .freq_tbl = ftbl_gcc_vsensor_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_vsensor_clk_src",
> + .parent_data = gcc_parent_data_9,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +
Extra empty line
> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
> + .halt_reg = 0x770c0,
> + .halt_check = BRANCH_HALT_VOTED,
[...]
> +
> +static struct clk_branch gcc_pcie_0_pipe_clk = {
> + .halt_reg = 0x6b024,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(4),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_pcie_0_pipe_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
No corresponding gcc_pcie_0_pipe_clk_src?
> +
> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> + .halt_reg = 0x6b014,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x6b014,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data) {
> + .name = "gcc_pcie_0_slv_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
[...]
--
With best wishes
Dmitry
On 9/20/2024 4:33 PM, Dmitry Baryshkov wrote:
> On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
>> Add the global clock controller support for QCS615 SoC.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>> drivers/clk/qcom/Kconfig | 9 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 3045 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index a3e2a09e2105..52a7ba6d4cbf 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -467,6 +467,15 @@ config QCS_GCC_404
>> Say Y if you want to use multimedia devices or peripheral
>> devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
>>
>> +config QCS_GCC_615
>> + tristate "QCS615 Global Clock Controller"
>> + depends on ARM64 || COMPILE_TEST
>> + select QCOM_GDSC
>> + help
>> + Support for the global clock controller on QCS615 devices.
>> + Say Y if you want to use multimedia devices or peripheral
>> + devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
>> +
>> config SC_CAMCC_7180
>> tristate "SC7180 Camera Clock Controller"
>> depends on ARM64 || COMPILE_TEST
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 2b378667a63f..a46ce0723602 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -70,6 +70,7 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
>> obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
>> obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
>> obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
>> +obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
>> obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
>> obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
>> obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
>> diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
>> new file mode 100644
>> index 000000000000..7db55a5d8e80
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-qcs615.c
>> @@ -0,0 +1,3035 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/mod_devicetable.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,qcs615-gcc.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "common.h"
>> +#include "gdsc.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + DT_BI_TCXO,
>> + DT_BI_TCXO_AO,
>> + DT_SLEEP_CLK,
>> +};
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_GPLL0_OUT_AUX2_DIV,
>> + P_GPLL0_OUT_MAIN,
>> + P_GPLL3_OUT_MAIN,
>> + P_GPLL3_OUT_MAIN_DIV,
>> + P_GPLL4_OUT_MAIN,
>> + P_GPLL6_OUT_MAIN,
>> + P_GPLL7_OUT_MAIN,
>> + P_GPLL8_OUT_MAIN,
>> + P_SLEEP_CLK,
>> +};
>> +
>> +static struct clk_alpha_pll gpll0 = {
>> + .offset = 0x0,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll0",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll0_out_aux2_div = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "gpll0_out_aux2_div",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .hw = &gpll0.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_fixed_factor_ops,
>> + },
>> +};
>
> Should it be clk_alpha_pll_postdiv_foo_ops ?
>
This is not the PLL output, but it is a fixed divider which is placed as
input to the RCG.
That is the reason to use the fixed factor.
>> +
>> +static struct clk_alpha_pll gpll3 = {
>> + .offset = 0x3000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(3),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll3",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll3_out_aux2_div = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data) {
>> + .name = "gpll3_out_aux2_div",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .hw = &gpll3.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_fixed_factor_ops,
>> + },
>> +};
>
> Should it be clk_alpha_pll_postdiv_foo_ops ?
>
Same is the case here as well. This is not the PLL output, but it is a
fixed divider which is placed as input to the RCG.
That is the reason to use the fixed factor.
>> +
>> +static struct clk_alpha_pll gpll4 = {
>> + .offset = 0x76000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll4",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll6 = {
>> + .offset = 0x13000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(6),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll6",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct clk_div_table post_div_table_gpll6_out_main[] = {
>> + { 0x1, 2 },
>> + { }
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll6_out_main = {
>> + .offset = 0x13000,
>> + .post_div_shift = 8,
>> + .post_div_table = post_div_table_gpll6_out_main,
>> + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
>> + .width = 4,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gpll6_out_main",
>> + .parent_hws = (const struct clk_hw*[]) {
>> + &gpll6.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll7 = {
>> + .offset = 0x1a000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(7),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll7",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll8 = {
>> + .offset = 0x1b000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr = {
>> + .enable_reg = 0x52000,
>> + .enable_mask = BIT(8),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gpll8",
>> + .parent_data = &(const struct clk_parent_data) {
>> + .index = DT_BI_TCXO,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static const struct clk_div_table post_div_table_gpll8_out_main[] = {
>> + { 0x1, 2 },
>> + { }
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll8_out_main = {
>> + .offset = 0x1b000,
>> + .post_div_shift = 8,
>> + .post_div_table = post_div_table_gpll8_out_main,
>> + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
>> + .width = 4,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gpll8_out_main",
>> + .parent_hws = (const struct clk_hw*[]) {
>> + &gpll8.clkr.hw,
>> + },
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_0[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_0_ao[] = {
>> + { .index = DT_BI_TCXO_AO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll0.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_1[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL6_OUT_MAIN, 2 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll6_out_main.clkr.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_2[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_2[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .index = DT_SLEEP_CLK },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_3[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> + { .index = DT_BI_TCXO },
>> + { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_4[] = {
>> + { P_BI_TCXO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>> + { .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_5[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL7_OUT_MAIN, 3 },
>> + { P_GPLL4_OUT_MAIN, 5 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_5[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll7.clkr.hw },
>> + { .hw = &gpll4.clkr.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_6[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL7_OUT_MAIN, 3 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_6[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll7.clkr.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_7[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL3_OUT_MAIN_DIV, 4 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_7[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll3_out_aux2_div.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_8[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL8_OUT_MAIN, 2 },
>> + { P_GPLL4_OUT_MAIN, 5 },
>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_8[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll8_out_main.clkr.hw },
>> + { .hw = &gpll4.clkr.hw },
>> + { .hw = &gpll0_out_aux2_div.hw },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_9[] = {
>> + { P_BI_TCXO, 0 },
>> + { P_GPLL0_OUT_MAIN, 1 },
>> + { P_GPLL3_OUT_MAIN, 4 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_9[] = {
>> + { .index = DT_BI_TCXO },
>> + { .hw = &gpll0.clkr.hw },
>> + { .hw = &gpll3.clkr.hw },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
>> + .cmd_rcgr = 0x48014,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_0,
>> + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_cpuss_ahb_clk_src",
>> + .parent_data = gcc_parent_data_0_ao,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
>> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
>> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_emac_ptp_clk_src = {
>> + .cmd_rcgr = 0x6038,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_5,
>> + .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_emac_ptp_clk_src",
>> + .parent_data = gcc_parent_data_5,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
>> + F(2500000, P_BI_TCXO, 1, 25, 192),
>> + F(5000000, P_BI_TCXO, 1, 25, 96),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
>> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
>> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
>> + .cmd_rcgr = 0x601c,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_6,
>> + .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_emac_rgmii_clk_src",
>> + .parent_data = gcc_parent_data_6,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
>> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp1_clk_src = {
>> + .cmd_rcgr = 0x64004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_gp1_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp2_clk_src = {
>> + .cmd_rcgr = 0x65004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_gp2_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gcc_gp3_clk_src = {
>> + .cmd_rcgr = 0x66004,
>> + .mnd_width = 8,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_2,
>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_gp3_clk_src",
>> + .parent_data = gcc_parent_data_2,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
>> + F(9600000, P_BI_TCXO, 2, 0, 0),
>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>> + .cmd_rcgr = 0x6b02c,
>> + .mnd_width = 16,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_3,
>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_pcie_0_aux_clk_src",
>> + .parent_data = gcc_parent_data_3,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>> + .ops = &clk_rcg2_ops,
>
> Should it be using shared ops?
> I think there are other clocks here which are usually
> clk_rcg2_shared_ops.
>
As the source frequency is derived from 19.2MHz, so I left it as the
normal RCG ops. I can update it in the next patch.
>> + },
>> +};
>> +
>
> [...]
>
>> +static struct clk_rcg2 gcc_vsensor_clk_src = {
>> + .cmd_rcgr = 0x7a018,
>> + .mnd_width = 0,
>> + .hid_width = 5,
>> + .parent_map = gcc_parent_map_9,
>> + .freq_tbl = ftbl_gcc_vsensor_clk_src,
>> + .clkr.hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_vsensor_clk_src",
>> + .parent_data = gcc_parent_data_9,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>> + .ops = &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +
>
> Extra empty line
>
Sure, will take care in the next patch.
>> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>> + .halt_reg = 0x770c0,
>> + .halt_check = BRANCH_HALT_VOTED,
>
> [...]
>
>> +
>> +static struct clk_branch gcc_pcie_0_pipe_clk = {
>> + .halt_reg = 0x6b024,
>> + .halt_check = BRANCH_HALT_SKIP,
>> + .clkr = {
>> + .enable_reg = 0x5200c,
>> + .enable_mask = BIT(4),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_pcie_0_pipe_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>
> No corresponding gcc_pcie_0_pipe_clk_src?
>
On QCS615 the pipe clock source is not required to be modelled as the
mux is default Power on reset is set to external pipe clock.
>> +
>> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
>> + .halt_reg = 0x6b014,
>> + .halt_check = BRANCH_HALT_VOTED,
>> + .hwcg_reg = 0x6b014,
>> + .hwcg_bit = 1,
>> + .clkr = {
>> + .enable_reg = 0x5200c,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data) {
>> + .name = "gcc_pcie_0_slv_axi_clk",
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>
> [...]
>
--
Thanks & Regards,
Taniya Das.
On Wed, Oct 16, 2024 at 09:40:07AM +0530, Taniya Das wrote:
>
>
> On 9/20/2024 4:33 PM, Dmitry Baryshkov wrote:
> > On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
> > > Add the global clock controller support for QCS615 SoC.
> > >
> > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> > > ---
> > > drivers/clk/qcom/Kconfig | 9 +
> > > drivers/clk/qcom/Makefile | 1 +
> > > drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 3045 insertions(+)
> > >
> > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> > > index a3e2a09e2105..52a7ba6d4cbf 100644
> > > --- a/drivers/clk/qcom/Kconfig
> > > +++ b/drivers/clk/qcom/Kconfig
> > > @@ -467,6 +467,15 @@ config QCS_GCC_404
> > > Say Y if you want to use multimedia devices or peripheral
> > > devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
> > > +config QCS_GCC_615
> > > + tristate "QCS615 Global Clock Controller"
> > > + depends on ARM64 || COMPILE_TEST
> > > + select QCOM_GDSC
> > > + help
> > > + Support for the global clock controller on QCS615 devices.
> > > + Say Y if you want to use multimedia devices or peripheral
> > > + devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
> > > +
> > > config SC_CAMCC_7180
> > > tristate "SC7180 Camera Clock Controller"
> > > depends on ARM64 || COMPILE_TEST
> > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> > > index 2b378667a63f..a46ce0723602 100644
> > > --- a/drivers/clk/qcom/Makefile
> > > +++ b/drivers/clk/qcom/Makefile
> > > @@ -70,6 +70,7 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> > > obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o
> > > obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
> > > obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
> > > +obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
> > > obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
> > > obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
> > > obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
> > > diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
> > > new file mode 100644
> > > index 000000000000..7db55a5d8e80
> > > --- /dev/null
> > > +++ b/drivers/clk/qcom/gcc-qcs615.c
> > > @@ -0,0 +1,3035 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> > > + */
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/module.h>
> > > +#include <linux/mod_devicetable.h>
> > > +#include <linux/of.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/regmap.h>
> > > +
> > > +#include <dt-bindings/clock/qcom,qcs615-gcc.h>
> > > +
> > > +#include "clk-alpha-pll.h"
> > > +#include "clk-branch.h"
> > > +#include "clk-rcg.h"
> > > +#include "clk-regmap.h"
> > > +#include "clk-regmap-divider.h"
> > > +#include "clk-regmap-mux.h"
> > > +#include "common.h"
> > > +#include "gdsc.h"
> > > +#include "reset.h"
> > > +
> > > +enum {
> > > + DT_BI_TCXO,
> > > + DT_BI_TCXO_AO,
> > > + DT_SLEEP_CLK,
> > > +};
> > > +
> > > +enum {
> > > + P_BI_TCXO,
> > > + P_GPLL0_OUT_AUX2_DIV,
> > > + P_GPLL0_OUT_MAIN,
> > > + P_GPLL3_OUT_MAIN,
> > > + P_GPLL3_OUT_MAIN_DIV,
> > > + P_GPLL4_OUT_MAIN,
> > > + P_GPLL6_OUT_MAIN,
> > > + P_GPLL7_OUT_MAIN,
> > > + P_GPLL8_OUT_MAIN,
> > > + P_SLEEP_CLK,
> > > +};
> > > +
> > > +static struct clk_alpha_pll gpll0 = {
> > > + .offset = 0x0,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(0),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll0",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static struct clk_fixed_factor gpll0_out_aux2_div = {
> > > + .mult = 1,
> > > + .div = 2,
> > > + .hw.init = &(struct clk_init_data) {
> > > + .name = "gpll0_out_aux2_div",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .hw = &gpll0.clkr.hw,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_fixed_factor_ops,
> > > + },
> > > +};
> >
> > Should it be clk_alpha_pll_postdiv_foo_ops ?
> >
>
> This is not the PLL output, but it is a fixed divider which is placed as
> input to the RCG.
> That is the reason to use the fixed factor.
Usually OUT_AUX2 is the PLL output, isn't it? Even by its name. See
gcc-qcm2290 / gcc-sm6115 and most of other clock controller drivers,
except gcc-sm6125. Maybe I don't understand the difference between the
two usecases. Is there a difference in the GCC / PLL design?
> > > +
> > > +static struct clk_alpha_pll gpll3 = {
> > > + .offset = 0x3000,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(3),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll3",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static struct clk_fixed_factor gpll3_out_aux2_div = {
> > > + .mult = 1,
> > > + .div = 2,
> > > + .hw.init = &(struct clk_init_data) {
> > > + .name = "gpll3_out_aux2_div",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .hw = &gpll3.clkr.hw,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_fixed_factor_ops,
> > > + },
> > > +};
> >
> > Should it be clk_alpha_pll_postdiv_foo_ops ?
> >
>
> Same is the case here as well. This is not the PLL output, but it is a fixed
> divider which is placed as input to the RCG.
> That is the reason to use the fixed factor.
>
> > > +
> > > +static struct clk_alpha_pll gpll4 = {
> > > + .offset = 0x76000,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(4),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll4",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static struct clk_alpha_pll gpll6 = {
> > > + .offset = 0x13000,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(6),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll6",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static const struct clk_div_table post_div_table_gpll6_out_main[] = {
> > > + { 0x1, 2 },
> > > + { }
> > > +};
> > > +
> > > +static struct clk_alpha_pll_postdiv gpll6_out_main = {
> > > + .offset = 0x13000,
> > > + .post_div_shift = 8,
> > > + .post_div_table = post_div_table_gpll6_out_main,
> > > + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
> > > + .width = 4,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll6_out_main",
> > > + .parent_hws = (const struct clk_hw*[]) {
> > > + &gpll6.clkr.hw,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_postdiv_ops,
> > > + },
> > > +};
> > > +
> > > +static struct clk_alpha_pll gpll7 = {
> > > + .offset = 0x1a000,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(7),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll7",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static struct clk_alpha_pll gpll8 = {
> > > + .offset = 0x1b000,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr = {
> > > + .enable_reg = 0x52000,
> > > + .enable_mask = BIT(8),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll8",
> > > + .parent_data = &(const struct clk_parent_data) {
> > > + .index = DT_BI_TCXO,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_ops,
> > > + },
> > > + },
> > > +};
> > > +
> > > +static const struct clk_div_table post_div_table_gpll8_out_main[] = {
> > > + { 0x1, 2 },
> > > + { }
> > > +};
> > > +
> > > +static struct clk_alpha_pll_postdiv gpll8_out_main = {
> > > + .offset = 0x1b000,
> > > + .post_div_shift = 8,
> > > + .post_div_table = post_div_table_gpll8_out_main,
> > > + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
> > > + .width = 4,
> > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gpll8_out_main",
> > > + .parent_hws = (const struct clk_hw*[]) {
> > > + &gpll8.clkr.hw,
> > > + },
> > > + .num_parents = 1,
> > > + .ops = &clk_alpha_pll_postdiv_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_0[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_0[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_0_ao[] = {
> > > + { .index = DT_BI_TCXO_AO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll0.clkr.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_1[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL6_OUT_MAIN, 2 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_1[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll6_out_main.clkr.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_2[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_SLEEP_CLK, 5 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_2[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .index = DT_SLEEP_CLK },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_3[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_SLEEP_CLK, 5 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_3[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .index = DT_SLEEP_CLK },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_4[] = {
> > > + { P_BI_TCXO, 0 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_4[] = {
> > > + { .index = DT_BI_TCXO },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_5[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL7_OUT_MAIN, 3 },
> > > + { P_GPLL4_OUT_MAIN, 5 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_5[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll7.clkr.hw },
> > > + { .hw = &gpll4.clkr.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_6[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL7_OUT_MAIN, 3 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_6[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll7.clkr.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_7[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL3_OUT_MAIN_DIV, 4 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_7[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll3_out_aux2_div.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_8[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL8_OUT_MAIN, 2 },
> > > + { P_GPLL4_OUT_MAIN, 5 },
> > > + { P_GPLL0_OUT_AUX2_DIV, 6 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_8[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll8_out_main.clkr.hw },
> > > + { .hw = &gpll4.clkr.hw },
> > > + { .hw = &gpll0_out_aux2_div.hw },
> > > +};
> > > +
> > > +static const struct parent_map gcc_parent_map_9[] = {
> > > + { P_BI_TCXO, 0 },
> > > + { P_GPLL0_OUT_MAIN, 1 },
> > > + { P_GPLL3_OUT_MAIN, 4 },
> > > +};
> > > +
> > > +static const struct clk_parent_data gcc_parent_data_9[] = {
> > > + { .index = DT_BI_TCXO },
> > > + { .hw = &gpll0.clkr.hw },
> > > + { .hw = &gpll3.clkr.hw },
> > > +};
> > > +
> > > +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
> > > + F(19200000, P_BI_TCXO, 1, 0, 0),
> > > + { }
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
> > > + .cmd_rcgr = 0x48014,
> > > + .mnd_width = 0,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_0,
> > > + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_cpuss_ahb_clk_src",
> > > + .parent_data = gcc_parent_data_0_ao,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
> > > + F(19200000, P_BI_TCXO, 1, 0, 0),
> > > + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> > > + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
> > > + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
> > > + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
> > > + { }
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_emac_ptp_clk_src = {
> > > + .cmd_rcgr = 0x6038,
> > > + .mnd_width = 0,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_5,
> > > + .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_emac_ptp_clk_src",
> > > + .parent_data = gcc_parent_data_5,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
> > > + F(2500000, P_BI_TCXO, 1, 25, 192),
> > > + F(5000000, P_BI_TCXO, 1, 25, 96),
> > > + F(19200000, P_BI_TCXO, 1, 0, 0),
> > > + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
> > > + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> > > + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
> > > + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
> > > + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
> > > + { }
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
> > > + .cmd_rcgr = 0x601c,
> > > + .mnd_width = 8,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_6,
> > > + .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_emac_rgmii_clk_src",
> > > + .parent_data = gcc_parent_data_6,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> > > + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
> > > + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
> > > + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
> > > + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> > > + { }
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_gp1_clk_src = {
> > > + .cmd_rcgr = 0x64004,
> > > + .mnd_width = 8,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_2,
> > > + .freq_tbl = ftbl_gcc_gp1_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_gp1_clk_src",
> > > + .parent_data = gcc_parent_data_2,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_gp2_clk_src = {
> > > + .cmd_rcgr = 0x65004,
> > > + .mnd_width = 8,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_2,
> > > + .freq_tbl = ftbl_gcc_gp1_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_gp2_clk_src",
> > > + .parent_data = gcc_parent_data_2,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_gp3_clk_src = {
> > > + .cmd_rcgr = 0x66004,
> > > + .mnd_width = 8,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_2,
> > > + .freq_tbl = ftbl_gcc_gp1_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_gp3_clk_src",
> > > + .parent_data = gcc_parent_data_2,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
> > > + F(9600000, P_BI_TCXO, 2, 0, 0),
> > > + F(19200000, P_BI_TCXO, 1, 0, 0),
> > > + { }
> > > +};
> > > +
> > > +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
> > > + .cmd_rcgr = 0x6b02c,
> > > + .mnd_width = 16,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_3,
> > > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_pcie_0_aux_clk_src",
> > > + .parent_data = gcc_parent_data_3,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> > > + .ops = &clk_rcg2_ops,
> >
> > Should it be using shared ops?
> > I think there are other clocks here which are usually
> > clk_rcg2_shared_ops.
> >
>
> As the source frequency is derived from 19.2MHz, so I left it as the normal
> RCG ops. I can update it in the next patch.
>
> > > + },
> > > +};
> > > +
> >
> > [...]
> >
> > > +static struct clk_rcg2 gcc_vsensor_clk_src = {
> > > + .cmd_rcgr = 0x7a018,
> > > + .mnd_width = 0,
> > > + .hid_width = 5,
> > > + .parent_map = gcc_parent_map_9,
> > > + .freq_tbl = ftbl_gcc_vsensor_clk_src,
> > > + .clkr.hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_vsensor_clk_src",
> > > + .parent_data = gcc_parent_data_9,
> > > + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> > > + .ops = &clk_rcg2_ops,
> > > + },
> > > +};
> > > +
> > > +
> >
> > Extra empty line
> >
> Sure, will take care in the next patch.
>
>
> > > +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
> > > + .halt_reg = 0x770c0,
> > > + .halt_check = BRANCH_HALT_VOTED,
> >
> > [...]
> >
> > > +
> > > +static struct clk_branch gcc_pcie_0_pipe_clk = {
> > > + .halt_reg = 0x6b024,
> > > + .halt_check = BRANCH_HALT_SKIP,
> > > + .clkr = {
> > > + .enable_reg = 0x5200c,
> > > + .enable_mask = BIT(4),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_pcie_0_pipe_clk",
> > > + .ops = &clk_branch2_ops,
> > > + },
> > > + },
> > > +};
> >
> > No corresponding gcc_pcie_0_pipe_clk_src?
> >
>
> On QCS615 the pipe clock source is not required to be modelled as the mux is
> default Power on reset is set to external pipe clock.
And do we need to toggle the source of the clk_src together with the
GDSC toggling?
>
> > > +
> > > +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> > > + .halt_reg = 0x6b014,
> > > + .halt_check = BRANCH_HALT_VOTED,
> > > + .hwcg_reg = 0x6b014,
> > > + .hwcg_bit = 1,
> > > + .clkr = {
> > > + .enable_reg = 0x5200c,
> > > + .enable_mask = BIT(0),
> > > + .hw.init = &(const struct clk_init_data) {
> > > + .name = "gcc_pcie_0_slv_axi_clk",
> > > + .ops = &clk_branch2_ops,
> > > + },
> > > + },
> > > +};
> > > +
> >
> > [...]
> >
>
> --
> Thanks & Regards,
> Taniya Das.
--
With best wishes
Dmitry
On 10/16/2024 3:46 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 16, 2024 at 09:40:07AM +0530, Taniya Das wrote:
>>
>>
>> On 9/20/2024 4:33 PM, Dmitry Baryshkov wrote:
>>> On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
>>>> Add the global clock controller support for QCS615 SoC.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>> drivers/clk/qcom/Kconfig | 9 +
>>>> drivers/clk/qcom/Makefile | 1 +
>>>> drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 3045 insertions(+)
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll gpll0 = {
>>>> + .offset = 0x0,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll0",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_fixed_factor gpll0_out_aux2_div = {
>>>> + .mult = 1,
>>>> + .div = 2,
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "gpll0_out_aux2_div",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .hw = &gpll0.clkr.hw,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_fixed_factor_ops,
>>>> + },
>>>> +};
>>>
>>> Should it be clk_alpha_pll_postdiv_foo_ops ?
>>>
>>
>> This is not the PLL output, but it is a fixed divider which is placed as
>> input to the RCG.
>> That is the reason to use the fixed factor.
>
> Usually OUT_AUX2 is the PLL output, isn't it? Even by its name. See
> gcc-qcm2290 / gcc-sm6115 and most of other clock controller drivers,
> except gcc-sm6125. Maybe I don't understand the difference between the
> two usecases. Is there a difference in the GCC / PLL design?
>
Yes, your understanding is correct out_aux2/out_main are the PLL leaf
outputs. But on QCS615 the PLL dividers are not used and thus the aux2
and the other leaf outputs are at the same frequency as the main output
of the VCO and instead there was a fixed divider placed after the PLL to
divide the VCO output. There was a GCC design change required to meet
timing closures.
>>>> +
>>>> +static struct clk_alpha_pll gpll3 = {
>>>> + .offset = 0x3000,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(3),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll3",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_fixed_factor gpll3_out_aux2_div = {
>>>> + .mult = 1,
>>>> + .div = 2,
>>>> + .hw.init = &(struct clk_init_data) {
>>>> + .name = "gpll3_out_aux2_div",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .hw = &gpll3.clkr.hw,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_fixed_factor_ops,
>>>> + },
>>>> +};
>>>
>>> Should it be clk_alpha_pll_postdiv_foo_ops ?
>>>
>>
>> Same is the case here as well. This is not the PLL output, but it is a fixed
>> divider which is placed as input to the RCG.
>> That is the reason to use the fixed factor.
>>
>>>> +
>>>> +static struct clk_alpha_pll gpll4 = {
>>>> + .offset = 0x76000,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(4),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll4",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll gpll6 = {
>>>> + .offset = 0x13000,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(6),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll6",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct clk_div_table post_div_table_gpll6_out_main[] = {
>>>> + { 0x1, 2 },
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll_postdiv gpll6_out_main = {
>>>> + .offset = 0x13000,
>>>> + .post_div_shift = 8,
>>>> + .post_div_table = post_div_table_gpll6_out_main,
>>>> + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
>>>> + .width = 4,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll6_out_main",
>>>> + .parent_hws = (const struct clk_hw*[]) {
>>>> + &gpll6.clkr.hw,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_postdiv_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll gpll7 = {
>>>> + .offset = 0x1a000,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(7),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll7",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll gpll8 = {
>>>> + .offset = 0x1b000,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr = {
>>>> + .enable_reg = 0x52000,
>>>> + .enable_mask = BIT(8),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll8",
>>>> + .parent_data = &(const struct clk_parent_data) {
>>>> + .index = DT_BI_TCXO,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct clk_div_table post_div_table_gpll8_out_main[] = {
>>>> + { 0x1, 2 },
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_alpha_pll_postdiv gpll8_out_main = {
>>>> + .offset = 0x1b000,
>>>> + .post_div_shift = 8,
>>>> + .post_div_table = post_div_table_gpll8_out_main,
>>>> + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
>>>> + .width = 4,
>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gpll8_out_main",
>>>> + .parent_hws = (const struct clk_hw*[]) {
>>>> + &gpll8.clkr.hw,
>>>> + },
>>>> + .num_parents = 1,
>>>> + .ops = &clk_alpha_pll_postdiv_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_0[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_0[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_0_ao[] = {
>>>> + { .index = DT_BI_TCXO_AO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_1[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL6_OUT_MAIN, 2 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll6_out_main.clkr.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_2[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_SLEEP_CLK, 5 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_2[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .index = DT_SLEEP_CLK },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_3[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_SLEEP_CLK, 5 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .index = DT_SLEEP_CLK },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_4[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_5[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL7_OUT_MAIN, 3 },
>>>> + { P_GPLL4_OUT_MAIN, 5 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_5[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll7.clkr.hw },
>>>> + { .hw = &gpll4.clkr.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_6[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL7_OUT_MAIN, 3 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_6[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll7.clkr.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_7[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL3_OUT_MAIN_DIV, 4 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_7[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll3_out_aux2_div.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_8[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL8_OUT_MAIN, 2 },
>>>> + { P_GPLL4_OUT_MAIN, 5 },
>>>> + { P_GPLL0_OUT_AUX2_DIV, 6 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_8[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll8_out_main.clkr.hw },
>>>> + { .hw = &gpll4.clkr.hw },
>>>> + { .hw = &gpll0_out_aux2_div.hw },
>>>> +};
>>>> +
>>>> +static const struct parent_map gcc_parent_map_9[] = {
>>>> + { P_BI_TCXO, 0 },
>>>> + { P_GPLL0_OUT_MAIN, 1 },
>>>> + { P_GPLL3_OUT_MAIN, 4 },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data gcc_parent_data_9[] = {
>>>> + { .index = DT_BI_TCXO },
>>>> + { .hw = &gpll0.clkr.hw },
>>>> + { .hw = &gpll3.clkr.hw },
>>>> +};
>>>> +
>>>> +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
>>>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
>>>> + .cmd_rcgr = 0x48014,
>>>> + .mnd_width = 0,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_0,
>>>> + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_cpuss_ahb_clk_src",
>>>> + .parent_data = gcc_parent_data_0_ao,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
>>>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>>>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>>>> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
>>>> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
>>>> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_emac_ptp_clk_src = {
>>>> + .cmd_rcgr = 0x6038,
>>>> + .mnd_width = 0,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_5,
>>>> + .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_emac_ptp_clk_src",
>>>> + .parent_data = gcc_parent_data_5,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
>>>> + F(2500000, P_BI_TCXO, 1, 25, 192),
>>>> + F(5000000, P_BI_TCXO, 1, 25, 96),
>>>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>>>> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
>>>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>>>> + F(75000000, P_GPLL0_OUT_AUX2_DIV, 4, 0, 0),
>>>> + F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
>>>> + F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
>>>> + .cmd_rcgr = 0x601c,
>>>> + .mnd_width = 8,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_6,
>>>> + .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_emac_rgmii_clk_src",
>>>> + .parent_data = gcc_parent_data_6,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
>>>> + F(25000000, P_GPLL0_OUT_AUX2_DIV, 12, 0, 0),
>>>> + F(50000000, P_GPLL0_OUT_AUX2_DIV, 6, 0, 0),
>>>> + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
>>>> + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_gp1_clk_src = {
>>>> + .cmd_rcgr = 0x64004,
>>>> + .mnd_width = 8,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_2,
>>>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_gp1_clk_src",
>>>> + .parent_data = gcc_parent_data_2,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_gp2_clk_src = {
>>>> + .cmd_rcgr = 0x65004,
>>>> + .mnd_width = 8,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_2,
>>>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_gp2_clk_src",
>>>> + .parent_data = gcc_parent_data_2,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_gp3_clk_src = {
>>>> + .cmd_rcgr = 0x66004,
>>>> + .mnd_width = 8,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_2,
>>>> + .freq_tbl = ftbl_gcc_gp1_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_gp3_clk_src",
>>>> + .parent_data = gcc_parent_data_2,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
>>>> + F(9600000, P_BI_TCXO, 2, 0, 0),
>>>> + F(19200000, P_BI_TCXO, 1, 0, 0),
>>>> + { }
>>>> +};
>>>> +
>>>> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
>>>> + .cmd_rcgr = 0x6b02c,
>>>> + .mnd_width = 16,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_3,
>>>> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_pcie_0_aux_clk_src",
>>>> + .parent_data = gcc_parent_data_3,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
>>>> + .ops = &clk_rcg2_ops,
>>>
>>> Should it be using shared ops?
>>> I think there are other clocks here which are usually
>>> clk_rcg2_shared_ops.
>>>
>>
>> As the source frequency is derived from 19.2MHz, so I left it as the normal
>> RCG ops. I can update it in the next patch.
>>
>>>> + },
>>>> +};
>>>> +
>>>
>>> [...]
>>>
>>>> +static struct clk_rcg2 gcc_vsensor_clk_src = {
>>>> + .cmd_rcgr = 0x7a018,
>>>> + .mnd_width = 0,
>>>> + .hid_width = 5,
>>>> + .parent_map = gcc_parent_map_9,
>>>> + .freq_tbl = ftbl_gcc_vsensor_clk_src,
>>>> + .clkr.hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_vsensor_clk_src",
>>>> + .parent_data = gcc_parent_data_9,
>>>> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
>>>> + .ops = &clk_rcg2_ops,
>>>> + },
>>>> +};
>>>> +
>>>> +
>>>
>>> Extra empty line
>>>
>> Sure, will take care in the next patch.
>>
>>
>>>> +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
>>>> + .halt_reg = 0x770c0,
>>>> + .halt_check = BRANCH_HALT_VOTED,
>>>
>>> [...]
>>>
>>>> +
>>>> +static struct clk_branch gcc_pcie_0_pipe_clk = {
>>>> + .halt_reg = 0x6b024,
>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>> + .clkr = {
>>>> + .enable_reg = 0x5200c,
>>>> + .enable_mask = BIT(4),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_pcie_0_pipe_clk",
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>
>>> No corresponding gcc_pcie_0_pipe_clk_src?
>>>
>>
>> On QCS615 the pipe clock source is not required to be modelled as the mux is
>> default Power on reset is set to external pipe clock.
>
> And do we need to toggle the source of the clk_src together with the
> GDSC toggling?
>
AFAIR, QCS615 didn't require toggling for GDSC, as even on downstream
kernel we do not have the pipe_clk_src modelled in our driver.
>>
>>>> +
>>>> +static struct clk_branch gcc_pcie_0_slv_axi_clk = {
>>>> + .halt_reg = 0x6b014,
>>>> + .halt_check = BRANCH_HALT_VOTED,
>>>> + .hwcg_reg = 0x6b014,
>>>> + .hwcg_bit = 1,
>>>> + .clkr = {
>>>> + .enable_reg = 0x5200c,
>>>> + .enable_mask = BIT(0),
>>>> + .hw.init = &(const struct clk_init_data) {
>>>> + .name = "gcc_pcie_0_slv_axi_clk",
>>>> + .ops = &clk_branch2_ops,
>>>> + },
>>>> + },
>>>> +};
>>>> +
>>>
>>> [...]
>>>
>>
>> --
>> Thanks & Regards,
>> Taniya Das.
>
--
Thanks & Regards,
Taniya Das.
On Fri, Oct 18, 2024 at 11:14:00PM +0530, Taniya Das wrote:
>
>
> On 10/16/2024 3:46 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 16, 2024 at 09:40:07AM +0530, Taniya Das wrote:
> > >
> > >
> > > On 9/20/2024 4:33 PM, Dmitry Baryshkov wrote:
> > > > On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
> > > > > Add the global clock controller support for QCS615 SoC.
> > > > >
> > > > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> > > > > ---
> > > > > drivers/clk/qcom/Kconfig | 9 +
> > > > > drivers/clk/qcom/Makefile | 1 +
> > > > > drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
> > > > > 3 files changed, 3045 insertions(+)
>
> > > > > +};
> > > > > +
> > > > > +static struct clk_alpha_pll gpll0 = {
> > > > > + .offset = 0x0,
> > > > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > > > > + .clkr = {
> > > > > + .enable_reg = 0x52000,
> > > > > + .enable_mask = BIT(0),
> > > > > + .hw.init = &(const struct clk_init_data) {
> > > > > + .name = "gpll0",
> > > > > + .parent_data = &(const struct clk_parent_data) {
> > > > > + .index = DT_BI_TCXO,
> > > > > + },
> > > > > + .num_parents = 1,
> > > > > + .ops = &clk_alpha_pll_ops,
> > > > > + },
> > > > > + },
> > > > > +};
> > > > > +
> > > > > +static struct clk_fixed_factor gpll0_out_aux2_div = {
> > > > > + .mult = 1,
> > > > > + .div = 2,
> > > > > + .hw.init = &(struct clk_init_data) {
> > > > > + .name = "gpll0_out_aux2_div",
> > > > > + .parent_data = &(const struct clk_parent_data) {
> > > > > + .hw = &gpll0.clkr.hw,
> > > > > + },
> > > > > + .num_parents = 1,
> > > > > + .ops = &clk_fixed_factor_ops,
> > > > > + },
> > > > > +};
> > > >
> > > > Should it be clk_alpha_pll_postdiv_foo_ops ?
> > > >
> > >
> > > This is not the PLL output, but it is a fixed divider which is placed as
> > > input to the RCG.
> > > That is the reason to use the fixed factor.
> >
> > Usually OUT_AUX2 is the PLL output, isn't it? Even by its name. See
> > gcc-qcm2290 / gcc-sm6115 and most of other clock controller drivers,
> > except gcc-sm6125. Maybe I don't understand the difference between the
> > two usecases. Is there a difference in the GCC / PLL design?
> >
>
> Yes, your understanding is correct out_aux2/out_main are the PLL leaf
> outputs. But on QCS615 the PLL dividers are not used and thus the aux2 and
> the other leaf outputs are at the same frequency as the main output of the
> VCO and instead there was a fixed divider placed after the PLL to divide the
> VCO output. There was a GCC design change required to meet timing closures.
Ack, please add a comment that this PLL uses fixed divider instead of
a normal postdiv (and to other out_aux2 clocks too).
> > > >
> > > > > +
> > > > > +static struct clk_branch gcc_pcie_0_pipe_clk = {
> > > > > + .halt_reg = 0x6b024,
> > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > > + .clkr = {
> > > > > + .enable_reg = 0x5200c,
> > > > > + .enable_mask = BIT(4),
> > > > > + .hw.init = &(const struct clk_init_data) {
> > > > > + .name = "gcc_pcie_0_pipe_clk",
> > > > > + .ops = &clk_branch2_ops,
> > > > > + },
> > > > > + },
> > > > > +};
> > > >
> > > > No corresponding gcc_pcie_0_pipe_clk_src?
> > > >
> > >
> > > On QCS615 the pipe clock source is not required to be modelled as the mux is
> > > default Power on reset is set to external pipe clock.
> >
> > And do we need to toggle the source of the clk_src together with the
> > GDSC toggling?
> >
>
> AFAIR, QCS615 didn't require toggling for GDSC, as even on downstream kernel
> we do not have the pipe_clk_src modelled in our driver.
OK, thanks for the explanation.
--
With best wishes
Dmitry
On 10/19/2024 12:16 AM, Dmitry Baryshkov wrote:
> On Fri, Oct 18, 2024 at 11:14:00PM +0530, Taniya Das wrote:
>>
>>
>> On 10/16/2024 3:46 PM, Dmitry Baryshkov wrote:
>>> On Wed, Oct 16, 2024 at 09:40:07AM +0530, Taniya Das wrote:
>>>>
>>>>
>>>> On 9/20/2024 4:33 PM, Dmitry Baryshkov wrote:
>>>>> On Fri, Sep 20, 2024 at 04:08:18PM GMT, Taniya Das wrote:
>>>>>> Add the global clock controller support for QCS615 SoC.
>>>>>>
>>>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>>>> ---
>>>>>> drivers/clk/qcom/Kconfig | 9 +
>>>>>> drivers/clk/qcom/Makefile | 1 +
>>>>>> drivers/clk/qcom/gcc-qcs615.c | 3035 +++++++++++++++++++++++++++++++++++++++++
>>>>>> 3 files changed, 3045 insertions(+)
>>
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_alpha_pll gpll0 = {
>>>>>> + .offset = 0x0,
>>>>>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0x52000,
>>>>>> + .enable_mask = BIT(0),
>>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "gpll0",
>>>>>> + .parent_data = &(const struct clk_parent_data) {
>>>>>> + .index = DT_BI_TCXO,
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_alpha_pll_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>> +
>>>>>> +static struct clk_fixed_factor gpll0_out_aux2_div = {
>>>>>> + .mult = 1,
>>>>>> + .div = 2,
>>>>>> + .hw.init = &(struct clk_init_data) {
>>>>>> + .name = "gpll0_out_aux2_div",
>>>>>> + .parent_data = &(const struct clk_parent_data) {
>>>>>> + .hw = &gpll0.clkr.hw,
>>>>>> + },
>>>>>> + .num_parents = 1,
>>>>>> + .ops = &clk_fixed_factor_ops,
>>>>>> + },
>>>>>> +};
>>>>>
>>>>> Should it be clk_alpha_pll_postdiv_foo_ops ?
>>>>>
>>>>
>>>> This is not the PLL output, but it is a fixed divider which is placed as
>>>> input to the RCG.
>>>> That is the reason to use the fixed factor.
>>>
>>> Usually OUT_AUX2 is the PLL output, isn't it? Even by its name. See
>>> gcc-qcm2290 / gcc-sm6115 and most of other clock controller drivers,
>>> except gcc-sm6125. Maybe I don't understand the difference between the
>>> two usecases. Is there a difference in the GCC / PLL design?
>>>
>>
>> Yes, your understanding is correct out_aux2/out_main are the PLL leaf
>> outputs. But on QCS615 the PLL dividers are not used and thus the aux2 and
>> the other leaf outputs are at the same frequency as the main output of the
>> VCO and instead there was a fixed divider placed after the PLL to divide the
>> VCO output. There was a GCC design change required to meet timing closures.
>
> Ack, please add a comment that this PLL uses fixed divider instead of
> a normal postdiv (and to other out_aux2 clocks too).
>
Thank you. Sure, will update the comment in the next patch set.
>>>>>
>>>>>> +
>>>>>> +static struct clk_branch gcc_pcie_0_pipe_clk = {
>>>>>> + .halt_reg = 0x6b024,
>>>>>> + .halt_check = BRANCH_HALT_SKIP,
>>>>>> + .clkr = {
>>>>>> + .enable_reg = 0x5200c,
>>>>>> + .enable_mask = BIT(4),
>>>>>> + .hw.init = &(const struct clk_init_data) {
>>>>>> + .name = "gcc_pcie_0_pipe_clk",
>>>>>> + .ops = &clk_branch2_ops,
>>>>>> + },
>>>>>> + },
>>>>>> +};
>>>>>
>>>>> No corresponding gcc_pcie_0_pipe_clk_src?
>>>>>
>>>>
>>>> On QCS615 the pipe clock source is not required to be modelled as the mux is
>>>> default Power on reset is set to external pipe clock.
>>>
>>> And do we need to toggle the source of the clk_src together with the
>>> GDSC toggling?
>>>
>>
>> AFAIR, QCS615 didn't require toggling for GDSC, as even on downstream kernel
>> we do not have the pipe_clk_src modelled in our driver.
>
> OK, thanks for the explanation.
>
--
Thanks & Regards,
Taniya Das.
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