Add dt-bindings for Everest Semi ES7243E ADC.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
---
 .../devicetree/bindings/sound/everest,es7243e.yaml | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/everest,es7243e.yaml b/Documentation/devicetree/bindings/sound/everest,es7243e.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..6afb467f389a70ad406a0fd953448b83b39ed858
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/everest,es7243e.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es7243e.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES7243E audio ADC
+
+maintainers:
+  - Igor Prusov <ivprusov@salutedevices.com>
+
+allOf:
+  - $ref: dai-common.yaml#
+
+properties:
+  compatible:
+    const: everest,es7243e
+
+  reg:
+    maxItems: 1
+
+  "#sound-dai-cells":
+    const: 0
+
+  clocks:
+    minItems: 2
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: sclk
+      - const: lrclk
+
+required:
+  - compatible
+  - reg
+  - "#sound-dai-cells"
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      es7243e: audio-codec@14 {
+        compatible = "everest,es7243e";
+        reg = <0x14>;
+        #sound-dai-cells = <0>;
+        clocks = <&clk_audio_sclk>,
+                 <&clk_audio_lrclk>;
+        clock-names = "sclk", "lrclk";
+      };
+    };

-- 
2.34.1

On Fri, Sep 20, 2024 at 06:41:07PM +0300, Igor Prusov wrote:

> +  clocks:
> +    minItems: 2
> +    maxItems: 2

> +  clock-names:
> +    items:
> +      - const: sclk
> +      - const: lrclk

This is quite weird and doesn't seem to correspond to the chip datasheet
at:

    http://www.everest-semi.com/pdf/ES7243%20PB.pdf
    https://www.pawpaw.cn/media/documents/2022-04/ES7243E_DS_pawpaw%E6%9C%A8%E7%93%9C%E7%A7%91%E6%8A%80.pdf

The SCLK and LRCLK appear to be the bit and frame sync clocks which
would not normally be exposed directly via the clock API (so this is
probably not going to be joined up with whatever SoC it's connected to).
On the other hand there *is* a MCLK which would much more normally be
represented in the DT bindings and isn't represented here or managed by
the driver.