arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ 11 files changed, 12 insertions(+), 1 deletion(-)
I only read back the SMMU config on X1E & 7280, but I have it on good authority that this concerns all RPMh SoCs. Sending as RFC just in case. Lacking coherency can hurt performance, but claiming coherency where it's absent would lead to a kaboom. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> --- Konrad Dybcio (11): arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ 11 files changed, 12 insertions(+), 1 deletion(-) --- base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 change-id: 20240919-topic-apps_smmu_coherent-070f38a2c207 Best regards, -- Konrad Dybcio <quic_kdybcio@quicinc.com>
On Thu, 19 Sep 2024 00:57:13 +0200, Konrad Dybcio wrote: > I only read back the SMMU config on X1E & 7280, but I have it on good > authority that this concerns all RPMh SoCs. Sending as RFC just in case. > > Lacking coherency can hurt performance, but claiming coherency where it's > absent would lead to a kaboom. > > > [...] Applied, thanks! [01/11] arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu commit: 7a52db70c8c5f4e2f6cf404b6cac10beae43f2bd [02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu commit: 3d89c1984000171665d8091c7fdf20f9cf814786 [03/11] arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu commit: 57222f077bd05b6ef8c5b2998400122f3c202e51 [04/11] arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu commit: 2b73b83cb82aefb6c907ea91a9977641bbcae683 [05/11] arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu commit: e009473c5f5d62d4e0f093a3126cf98e319d8cd0 [06/11] arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu commit: 6b31a9744b8726c69bb0af290f8475a368a4b805 [07/11] arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu commit: 7abe72765d9f6a900a1c2b6c12b9dd70010a8b0b [08/11] arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu commit: 05bd9923d15e8508cd0fa4f3d03437df1a9362aa [09/11] arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu commit: 051ff563cb3d87c631c8997d9b3636a7b59a12b9 [10/11] arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu commit: c9ab6652769d331e39f7489241e8b3427f7e8608 [11/11] arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu commit: 5207d9c75f18db46ce42074f6585c7ca8e4aca75 Best regards, -- Bjorn Andersson <andersson@kernel.org>
On 19/09/2024 00:57, Konrad Dybcio wrote: > I only read back the SMMU config on X1E & 7280, but I have it on good > authority that this concerns all RPMh SoCs. Sending as RFC just in case. > > Lacking coherency can hurt performance, but claiming coherency where it's > absent would lead to a kaboom. > > Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> > --- > Konrad Dybcio (11): > arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + > arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + > arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + > arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ > 11 files changed, 12 insertions(+), 1 deletion(-) > --- > base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 > change-id: 20240919-topic-apps_smmu_coherent-070f38a2c207 > > Best regards, Ran this serie in our CI, here's the pipeline: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba-tester/-/pipelines/104656 For some lab reasons, x1e80100 & onneplus-enchilada didn't boot, ignore them. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3 Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8150-hdk Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8350-hdk Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sm8450-hdk Neil
On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote: > I only read back the SMMU config on X1E & 7280, but I have it on good > authority that this concerns all RPMh SoCs. Sending as RFC just in case. > > Lacking coherency can hurt performance, but claiming coherency where it's > absent would lead to a kaboom. Hi Konrad! You want people with the affected SoCs to test this I imagine? Just boot it and see if it doesn't implode, or do you have any more elaborate test plan for this? Regards Luca > > Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> > --- > Konrad Dybcio (11): > arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu > arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu > > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + > arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + > arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + > arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + > arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + > arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ > 11 files changed, 12 insertions(+), 1 deletion(-) > --- > base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 > change-id: 20240919-topic-apps_smmu_coherent-070f38a2c207 > > Best regards,
On 19.09.2024 9:00 AM, Luca Weiss wrote: > On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote: >> I only read back the SMMU config on X1E & 7280, but I have it on good >> authority that this concerns all RPMh SoCs. Sending as RFC just in case. >> >> Lacking coherency can hurt performance, but claiming coherency where it's >> absent would lead to a kaboom. > > Hi Konrad! > > You want people with the affected SoCs to test this I imagine? Yeah, would be nice to confirm > > Just boot it and see if it doesn't implode, or do you have any more > elaborate test plan for this? No, booting should be enough of a test Konrad
Hi Konrad, On Thu, Sep 19, 2024 at 5:07 AM Konrad Dybcio <konradybcio@kernel.org> wrote: > > On 19.09.2024 9:00 AM, Luca Weiss wrote: > > On Thu Sep 19, 2024 at 12:57 AM CEST, Konrad Dybcio wrote: > >> I only read back the SMMU config on X1E & 7280, but I have it on good > >> authority that this concerns all RPMh SoCs. Sending as RFC just in case. > >> > >> Lacking coherency can hurt performance, but claiming coherency where it's > >> absent would lead to a kaboom. > > > > Hi Konrad! > > > > You want people with the affected SoCs to test this I imagine? > > Yeah, would be nice to confirm > > > > > Just boot it and see if it doesn't implode, or do you have any more > > elaborate test plan for this? > > No, booting should be enough of a test > > Konrad I have tested sc8280xp on the Thinkpad X13s. It still boots and nothing seems to be more broken than usual (kidding, it seems to be running exactly as it was before the patchset was applied.) I will try to find the time to test sc8180x on a Flex 5G as well as the sdm845 on the Lenovo Yoga C630, but I can't promise I'll find the time. Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
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