AMD SPI controller’s index mode performance is constrained by the hardware
limitation of the FIFO queue length. This patch series introduces
optimizations to the spi_amd driver, aiming to maximize throughput and
enhance overall performance. The changes includes,

- Enabling SPI dual and quad I/O modes
- Optimize I/O operations using efficient kernel APIs
- Optimize I/O operations by optimizing set tx/rx count functions
- Optimize I/O operations by reducing the data read calls to fetch the
data from FIFO queues
- Add changes to support AMD HID2 SPI controller
- Add changes to enhance SPI-MEM support functions to reflect hardware
capabilities
- Add changes to set SPI controller address mode before initiating the
commands
- Add changes to implement HIDDMA read operation support for HID2 SPI
controller

Raju Rangoju (9):
  spi: spi_amd: Sort headers alphabetically
  spi: spi_amd: Enable dual and quad I/O modes
  spi: spi_amd: Replace ioread/iowrite calls
  spi: spi_amd: Updates to set tx/rx count functions
  spi: spi_amd: Optimize IO operations
  spi: spi_amd: Add support for HID2 SPI controller
  spi: spi_amd: Enhance SPI-MEM support functions
  spi: spi_amd: Set controller address mode
  spi: spi_amd: Add HIDDMA basic read support

 drivers/spi/spi-amd.c | 325 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 295 insertions(+), 30 deletions(-)

-- 
2.34.1