Hi,

This series adds 16.0 GT/s specific equalization and RX lane margining settings
to the Qcom RC and EP drivers. This series is mandatory for the stable operation
of the PCIe link at 16.0 GT/s on the Qcom platforms.

NOTE:
=====

I've taken over the series from Shashank based on the discussion [1]. In order
to apply the equalization/margining settings properly in the Qcom driver, I
added the first 2 patches to the series which inevitably touches other vendor
drivers also.

- Mani

Changes in v7:
- Fixed the build issue reported by Kbuild bot in patch 1/4
- Changed the logic to check invalid max_link_speed in patch 2/4
- Cleanups to patches 3/4 and 4/4 as suggested by Johan
- Added include header guard to pci-qcom-common.h
- Link to v6: https://lore.kernel.org/r/20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org

Changes in v6:

- Dropped the code refactoring patch as suggested by Johan
- Added 2 patches to fix the caching of maximum supported link speed value that
  is needed to apply the equalization/margining settings
- Updated the commit message of patch 3 as per Bjorn's suggestion

For previous changelogs, please refer [2]

[1] https://lore.kernel.org/linux-pci/af65b744-7538-4929-9ab4-8ee42e17b8d1@quicinc.com/
[2] https://lore.kernel.org/linux-pci/20240821170917.21018-1-quic_schintav@quicinc.com/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Manivannan Sadhasivam (2):
      PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
      PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed

Shashank Babu Chinta Venkata (2):
      PCI: qcom: Add equalization settings for 16.0 GT/s
      PCI: qcom: Add RX lane margining settings for 16.0 GT/s

 MAINTAINERS                                   |  4 +-
 drivers/pci/controller/dwc/Kconfig            |  5 ++
 drivers/pci/controller/dwc/Makefile           |  1 +
 drivers/pci/controller/dwc/pci-imx6.c         |  8 +--
 drivers/pci/controller/dwc/pcie-designware.c  | 22 +++++---
 drivers/pci/controller/dwc/pcie-designware.h  | 33 +++++++++++-
 drivers/pci/controller/dwc/pcie-intel-gw.c    |  4 +-
 drivers/pci/controller/dwc/pcie-qcom-common.c | 78 +++++++++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom-common.h | 14 +++++
 drivers/pci/controller/dwc/pcie-qcom-ep.c     |  6 +++
 drivers/pci/controller/dwc/pcie-qcom.c        |  6 +++
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  6 +--
 drivers/pci/controller/dwc/pcie-spear13xx.c   |  2 +-
 drivers/pci/controller/dwc/pcie-tegra194.c    | 19 +++----
 14 files changed, 178 insertions(+), 30 deletions(-)
---
base-commit: 47ac09b91befbb6a235ab620c32af719f8208399
change-id: 20240904-pci-qcom-gen4-stability-02ec65a7e6e4

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Hello,

> This series adds 16.0 GT/s specific equalization and RX lane margining settings
> to the Qcom RC and EP drivers. This series is mandatory for the stable operation
> of the PCIe link at 16.0 GT/s on the Qcom platforms.
> 
> NOTE:
> =====
> 
> I've taken over the series from Shashank based on the discussion [1]. In order
> to apply the equalization/margining settings properly in the Qcom driver, I
> added the first 2 patches to the series which inevitably touches other vendor
> drivers also.

Applied to controller/qcom, thank you!

[01/04] PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
        https://git.kernel.org/pci/pci/c/2cebf68a24ab

[02/04] PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
        https://git.kernel.org/pci/pci/c/19a69cbd9d43

[03/04] PCI: qcom: Add equalization settings for 16.0 GT/s
        https://git.kernel.org/pci/pci/c/d45736b59849

[04/04] PCI: qcom: Add RX lane margining settings for 16.0 GT/s
        https://git.kernel.org/pci/pci/c/d14bc28af34f

	Krzysztof

On Wed, Sep 11, 2024 at 08:56:25PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> This series adds 16.0 GT/s specific equalization and RX lane margining settings
> to the Qcom RC and EP drivers. This series is mandatory for the stable operation
> of the PCIe link at 16.0 GT/s on the Qcom platforms.

> Manivannan Sadhasivam (2):
>       PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
>       PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
> 
> Shashank Babu Chinta Venkata (2):
>       PCI: qcom: Add equalization settings for 16.0 GT/s
>       PCI: qcom: Add RX lane margining settings for 16.0 GT/s

Thanks for respinning, Mani.

Bjorn, it would be great to have these in 6.12 since we're currently
seeing lots of NVMe link errors on x1e80100 platforms (e.g. the Lenovo
ThinkPad T14s) without them.

These errors are also blocking the enabling of using the GIC ITS for
interrupts since that will cause all these AER reports to spam the
logs. So if you pick this one up, please consider also picking up:

	https://lore.kernel.org/lkml/20240711090250.20827-1-johan+linaro@kernel.org/

[ Note that the later added PCIe5 RC does not currently support ITS. ]

Also note that users of these machines have been running with ITS
support enabled for months now when using my x1e80100 wip branches, such
as:

	https://github.com/jhovold/linux/tree/wip/x1e80100-6.11-rc7

So this is all quite well-tested by now.

Johan

On Thu, Sep 12, 2024 at 08:25:37AM +0200, Johan Hovold wrote:

> Bjorn, it would be great to have these in 6.12 since we're currently
> seeing lots of NVMe link errors on x1e80100 platforms (e.g. the Lenovo
> ThinkPad T14s) without them.
> 
> These errors are also blocking the enabling of using the GIC ITS for
> interrupts since that will cause all these AER reports to spam the
> logs. So if you pick this one up, please consider also picking up:
> 
> 	https://lore.kernel.org/lkml/20240711090250.20827-1-johan+linaro@kernel.org/

Heh, this one should of course go through the qcom tree once the Gen4
stability fixes have been merged by you. Sorry about the confusion.

Johan