On brcm_pcie_turn_off avoid shutdown of bridge reset.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
 drivers/pci/controller/pcie-brcmstb.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index d78f33b33884..185ccf7fe86a 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -234,10 +234,17 @@ struct inbound_win {
 	u64 cpu_addr;
 };
 
+/*
+ * Shutting down this bridge on pcie1 means accesses to rescal block
+ * will hang the chip if another RC wants to assert/deassert rescal.
+ */
+#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN		BIT(0)
+
 struct pcie_cfg_data {
 	const int *offsets;
 	const enum pcie_soc_base soc_base;
 	const bool has_phy;
+	const u32 quirks;
 	u8 num_inbound_wins;
 	int (*perst_set)(struct brcm_pcie *pcie, u32 val);
 	int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
@@ -290,6 +297,7 @@ struct brcm_pcie {
 	struct subdev_regulators *sr;
 	bool			ep_wakeup_capable;
 	bool			has_phy;
+	u32			quirks;
 	u8			num_inbound_wins;
 };
 
@@ -1549,8 +1557,9 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie)
 	u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
 	writel(tmp, base + HARD_DEBUG(pcie));
 
-	/* Shutdown PCIe bridge */
-	ret = pcie->bridge_sw_init_set(pcie, 1);
+	if (!(pcie->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN))
+		/* Shutdown PCIe bridge */
+		ret = pcie->bridge_sw_init_set(pcie, 1);
 
 	return ret;
 }
@@ -1864,6 +1873,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 	pcie->perst_set = data->perst_set;
 	pcie->bridge_sw_init_set = data->bridge_sw_init_set;
 	pcie->has_phy = data->has_phy;
+	pcie->quirks = data->quirks;
 	pcie->num_inbound_wins = data->num_inbound_wins;
 
 	pcie->base = devm_platform_ioremap_resource(pdev, 0);
-- 
2.35.3

On 9/10/24 08:18, Stanimir Varbanov wrote:
> On brcm_pcie_turn_off avoid shutdown of bridge reset.
> 
> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
> ---
>   drivers/pci/controller/pcie-brcmstb.c | 14 ++++++++++++--
>   1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d78f33b33884..185ccf7fe86a 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -234,10 +234,17 @@ struct inbound_win {
>   	u64 cpu_addr;
>   };
>   
> +/*
> + * Shutting down this bridge on pcie1 means accesses to rescal block
> + * will hang the chip if another RC wants to assert/deassert rescal.
> + */

Maybe a slightly more detailed comment saying that the RESCAL block is 
tied to PCIe controller #1, regardless of the number of controllers, and 
turning off PCIe controller #1 prevents access to the RESCAL register 
blocks, therefore not other controller can access this register space, 
and depending upon the bus fabric we may get a timeout (UBUS/GISB), or a 
hang (AXI).

Thanks!
-- 
Florian

On 9/10/24 20:03, Florian Fainelli wrote:
> On 9/10/24 08:18, Stanimir Varbanov wrote:
>> On brcm_pcie_turn_off avoid shutdown of bridge reset.
>>
>> Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
>> ---
>>   drivers/pci/controller/pcie-brcmstb.c | 14 ++++++++++++--
>>   1 file changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pci/controller/pcie-brcmstb.c
>> b/drivers/pci/controller/pcie-brcmstb.c
>> index d78f33b33884..185ccf7fe86a 100644
>> --- a/drivers/pci/controller/pcie-brcmstb.c
>> +++ b/drivers/pci/controller/pcie-brcmstb.c
>> @@ -234,10 +234,17 @@ struct inbound_win {
>>       u64 cpu_addr;
>>   };
>>   +/*
>> + * Shutting down this bridge on pcie1 means accesses to rescal block
>> + * will hang the chip if another RC wants to assert/deassert rescal.
>> + */
> 
> Maybe a slightly more detailed comment saying that the RESCAL block is
> tied to PCIe controller #1, regardless of the number of controllers, and
> turning off PCIe controller #1 prevents access to the RESCAL register
> blocks, therefore not other controller can access this register space,
> and depending upon the bus fabric we may get a timeout (UBUS/GISB), or a
> hang (AXI).

Ack. Thank you!

regards,
~Stan