.../boot/dts/mediatek/mt8395-genio-1200-evk.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator
supply settings and enable the GPU node.
In addition, set the GPU related regulator voltage range:
1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V),
based on Table 5-3 of MT8395 Application Processor Datasheet.
The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input.
2. Set the input voltage of DVDD_SRAM_GPU, supplied by
mt6359_vsram_others_ldo_reg, to 0.75V and set it always on for GPU SRAM.
This patch is tested by enabling CONFIG_DRM_PANFROST and
on Genio 1200 EVK it probed with following dmesg:
```
panfrost 13000000.gpu: clock rate = 700000092
panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0
panfrost 13000000.gpu: features: 00000000,000019f7,
issues: 00000001,80000400
panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000
Tiler:0x00000809 Mem:0x301
MMU:0x00002830 AS:0xff JS:0x7
panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
[drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0
```
Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
---
.../boot/dts/mediatek/mt8395-genio-1200-evk.dts | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index a06610fff8ad..9b7850b0b9b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -194,6 +194,11 @@ eth_phy0: eth-phy0@1 {
};
};
+&gpu {
+ mali-supply = <&mt6315_7_vbuck1>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
@@ -407,6 +412,13 @@ &mt6359_vrf12_ldo_reg {
regulator-always-on;
};
+/* for GPU SRAM */
+&mt6359_vsram_others_ldo_reg {
+ regulator-always-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+};
+
&mt6359codec {
mediatek,mic-type-0 = <1>; /* ACC */
mediatek,mic-type-1 = <3>; /* DCC */
@@ -839,8 +851,8 @@ regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1193750>;
+ regulator-min-microvolt = <546000>;
+ regulator-max-microvolt = <787000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};
--
2.45.2Il 10/09/24 16:32, Pablo Sun ha scritto:
> Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator
> supply settings and enable the GPU node.
>
> In addition, set the GPU related regulator voltage range:
>
> 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V),
> based on Table 5-3 of MT8395 Application Processor Datasheet.
> The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input.
> 2. Set the input voltage of DVDD_SRAM_GPU, supplied by
> mt6359_vsram_others_ldo_reg, to 0.75V and set it always on for GPU SRAM.
>
> This patch is tested by enabling CONFIG_DRM_PANFROST and
> on Genio 1200 EVK it probed with following dmesg:
>
> ```
> panfrost 13000000.gpu: clock rate = 700000092
> panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0
> panfrost 13000000.gpu: features: 00000000,000019f7,
> issues: 00000001,80000400
> panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000
> Tiler:0x00000809 Mem:0x301
> MMU:0x00002830 AS:0xff JS:0x7
> panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1
> [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0
> ```
>
> Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
> ---
> .../boot/dts/mediatek/mt8395-genio-1200-evk.dts | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
> index a06610fff8ad..9b7850b0b9b4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
> @@ -194,6 +194,11 @@ eth_phy0: eth-phy0@1 {
> };
> };
>
> +&gpu {
> + mali-supply = <&mt6315_7_vbuck1>;
> + status = "okay";
> +};
> +
> &i2c0 {
> clock-frequency = <400000>;
> pinctrl-0 = <&i2c0_pins>;
> @@ -407,6 +412,13 @@ &mt6359_vrf12_ldo_reg {
> regulator-always-on;
> };
>
> +/* for GPU SRAM */
> +&mt6359_vsram_others_ldo_reg {
> + regulator-always-on;
No, that's not good. Like that, the GPU VSRAM will be subject to current leakage.
Remove the regulator-always-on property.
The right way of doing that is to add the vgpu to the mfg0's domain supply and
vsram to mfg1; that way all of the GPU regulators will be off at PM suspend time.
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <750000>;
> +};
> +
> &mt6359codec {
> mediatek,mic-type-0 = <1>; /* ACC */
> mediatek,mic-type-1 = <3>; /* DCC */
> @@ -839,8 +851,8 @@ regulators {
> mt6315_7_vbuck1: vbuck1 {
> regulator-compatible = "vbuck1";
> regulator-name = "Vgpu";
> - regulator-min-microvolt = <300000>;
> - regulator-max-microvolt = <1193750>;
> + regulator-min-microvolt = <546000>;
I'm okay with this constraint but are you sure that MTK-SVS won't go any lower
than 0.546V?
Cheers,
Angelo
> + regulator-max-microvolt = <787000>;
> regulator-enable-ramp-delay = <256>;
> regulator-allowed-modes = <0 1 2>;
> };
Hi Angelo,
Thanks for the review,
On 9/11/24 16:57, AngeloGioacchino Del Regno wrote:
[snip]
>> +/* for GPU SRAM */
>> +&mt6359_vsram_others_ldo_reg {
>> + regulator-always-on;
>
> No, that's not good. Like that, the GPU VSRAM will be subject to current
> leakage.
>
> Remove the regulator-always-on property.
> The right way of doing that is to add the vgpu to the mfg0's domain
> supply and
> vsram to mfg1; that way all of the GPU regulators will be off at PM
> suspend time.
Thanks for pointing this out, I'll send v2 to fix this.
>> &mt6359codec {
>> mediatek,mic-type-0 = <1>; /* ACC */
>> mediatek,mic-type-1 = <3>; /* DCC */
>> @@ -839,8 +851,8 @@ regulators {
>> mt6315_7_vbuck1: vbuck1 {
>> regulator-compatible = "vbuck1";
>> regulator-name = "Vgpu";
>> - regulator-min-microvolt = <300000>;
>> - regulator-max-microvolt = <1193750>;
>> + regulator-min-microvolt = <546000>;
>
> I'm okay with this constraint but are you sure that MTK-SVS won't go any
> lower than 0.546V?
I'll see if I could confirm the maximum voltage drop that may be lowered
by mtk-svs for MT8395. There are 3 constraints that I am aware of:
- capability of Vgpu buck: 0.3V-1.193V
- sign-off voltage of the EVK board: 0.6V to 1.2V
- recommended operating voltage of MT8395 DVDD_GPU: 0.546V to 0.787V
For the device tree of the board, would you recommend set the regulator
voltage constraints in narrower range (because it's safer to keep in
recommended operating conditions), or in a wider range (leaving the
check to driver software for potential power saving?)
Thanks
Il 11/09/24 12:35, Pablo Sun ha scritto:
> Hi Angelo,
>
> Thanks for the review,
>
> On 9/11/24 16:57, AngeloGioacchino Del Regno wrote:
>
> [snip]
>
>>> +/* for GPU SRAM */
>>> +&mt6359_vsram_others_ldo_reg {
>>> + regulator-always-on;
>>
>> No, that's not good. Like that, the GPU VSRAM will be subject to current leakage.
>>
>> Remove the regulator-always-on property.
>> The right way of doing that is to add the vgpu to the mfg0's domain supply and
>> vsram to mfg1; that way all of the GPU regulators will be off at PM suspend time.
>
> Thanks for pointing this out, I'll send v2 to fix this.
>
>>> &mt6359codec {
>>> mediatek,mic-type-0 = <1>; /* ACC */
>>> mediatek,mic-type-1 = <3>; /* DCC */
>>> @@ -839,8 +851,8 @@ regulators {
>>> mt6315_7_vbuck1: vbuck1 {
>>> regulator-compatible = "vbuck1";
>>> regulator-name = "Vgpu";
>>> - regulator-min-microvolt = <300000>;
>>> - regulator-max-microvolt = <1193750>;
>>> + regulator-min-microvolt = <546000>;
>>
>> I'm okay with this constraint but are you sure that MTK-SVS won't go any lower
>> than 0.546V?
>
> I'll see if I could confirm the maximum voltage drop that may be lowered by mtk-svs
> for MT8395. There are 3 constraints that I am aware of:
>
> - capability of Vgpu buck: 0.3V-1.193V
> - sign-off voltage of the EVK board: 0.6V to 1.2V
> - recommended operating voltage of MT8395 DVDD_GPU: 0.546V to 0.787V
>
> For the device tree of the board, would you recommend set the regulator voltage
> constraints in narrower range (because it's safer to keep in recommended operating
> conditions), or in a wider range (leaving the check to driver software for
> potential power saving?)
>
The range should match the target device's Vin constraints; in this case, it
should be no lower than the minimum working voltage of the Vgpu-in of the Mali IP.
The drivers will be responsible of setting the lowest possible voltage for
enhanced efficiency (power saving), taking into account the fused chip quality bits
(in this case, the MediaTek SVS driver!).
You should, at this point, check the constraints of SVS, as in, given a reference
voltage (in this case, located in the GPU OPP table, the voltage associated with
the lowest frequency of the GPU), what is the maximum voltage *subtraction* that
SVS will do on the VGPU?
After the subtraction, may this voltage be lower than 0.546V? :-)
Cheers,
Angelo
> Thanks
>
>
Hi Angelo, On 9/12/24 15:52, AngeloGioacchino Del Regno wrote: [snip] >> > > The range should match the target device's Vin constraints; in this > case, it > should be no lower than the minimum working voltage of the Vgpu-in of > the Mali IP. > > The drivers will be responsible of setting the lowest possible voltage for > enhanced efficiency (power saving), taking into account the fused chip > quality bits > (in this case, the MediaTek SVS driver!). > > You should, at this point, check the constraints of SVS, as in, given a > reference > voltage (in this case, located in the GPU OPP table, the voltage > associated with > the lowest frequency of the GPU), what is the maximum voltage > *subtraction* that > SVS will do on the VGPU? > > After the subtraction, may this voltage be lower than 0.546V? :-) Thanks for the clear explanation. While there are no explicit constraint in the maximum voltage subtraction in the SVS driver, I have confirmed that the fuse data of MT8395 is written in a way that the SVS driver would never go lower than the minimum recommended operating voltage of DVDD_GPU in the datasheet[1], which supplies power to the Mali IP. I have sent patch v2 to remove the always-on property and add a note about the fuse(eFuse) data in [2]. [1]: https://mediatek-marketing.files.svdcdn.com/production/documents/MTK_MT8395_Application-Processor-Datasheet_v1.8.pdf?dm=1724252510 [2]: https://lkml.org/lkml/2024/9/12/285 Many thanks, Pablo
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