In case of OWL S900 SoC clock driver there are cases
where bfreq = 24000000, shift = 0. If value read from
CMU_COREPLL or CMU_DDRPLL to val is big enough, an
overflow may occur.

Add explicit casting to prevent it.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: 2792c37e94c8 ("clk: actions: Add pll clock support")
Cc: <stable@vger.kernel.org> 
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
---
 drivers/clk/actions/owl-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
index 155f313986b4..fa17567665ec 100644
--- a/drivers/clk/actions/owl-pll.c
+++ b/drivers/clk/actions/owl-pll.c
@@ -104,7 +104,7 @@ static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
 	val = val >> pll_hw->shift;
 	val &= mul_mask(pll_hw);
 
-	return pll_hw->bfreq * val;
+	return (unsigned long)pll_hw->bfreq * val;
 }
 
 static int owl_pll_is_enabled(struct clk_hw *hw)
-- 
2.30.2

Quoting Anastasia Belova (2024-09-10 06:06:40)
> In case of OWL S900 SoC clock driver there are cases
> where bfreq = 24000000, shift = 0. If value read from
> CMU_COREPLL or CMU_DDRPLL to val is big enough, an
> overflow may occur.
> 
> Add explicit casting to prevent it.
> 
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
> 
> Fixes: 2792c37e94c8 ("clk: actions: Add pll clock support")
> Cc: <stable@vger.kernel.org> 

Seems like we don't need these tags because it can't overflow.

> Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
> ---
>  drivers/clk/actions/owl-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
> index 155f313986b4..fa17567665ec 100644
> --- a/drivers/clk/actions/owl-pll.c
> +++ b/drivers/clk/actions/owl-pll.c
> @@ -104,7 +104,7 @@ static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
>         val = val >> pll_hw->shift;
>         val &= mul_mask(pll_hw);
>  
> -       return pll_hw->bfreq * val;
> +       return (unsigned long)pll_hw->bfreq * val;

I'm lost. Did you intend to cast this to a u64?

On Tue, Sep 10, 2024 at 04:06:40PM +0300, Anastasia Belova wrote:
> In case of OWL S900 SoC clock driver there are cases
> where bfreq = 24000000, shift = 0. If value read from
> CMU_COREPLL or CMU_DDRPLL to val is big enough, an
> overflow may occur.
> 
> Add explicit casting to prevent it.
> 
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
> 
> Fixes: 2792c37e94c8 ("clk: actions: Add pll clock support")
> Cc: <stable@vger.kernel.org> 
> Signed-off-by: Anastasia Belova <abelova@astralinux.ru>

Currently, val is limited to 8 bits max on the supported SoCs. So there won't be
any overflow. But for the sake of correctness, I'm OK with this patch.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  drivers/clk/actions/owl-pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/actions/owl-pll.c b/drivers/clk/actions/owl-pll.c
> index 155f313986b4..fa17567665ec 100644
> --- a/drivers/clk/actions/owl-pll.c
> +++ b/drivers/clk/actions/owl-pll.c
> @@ -104,7 +104,7 @@ static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
>  	val = val >> pll_hw->shift;
>  	val &= mul_mask(pll_hw);
>  
> -	return pll_hw->bfreq * val;
> +	return (unsigned long)pll_hw->bfreq * val;
>  }
>  
>  static int owl_pll_is_enabled(struct clk_hw *hw)
> -- 
> 2.30.2
> 

-- 
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