Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is
enabled by bit 11 in UCON.
Access these bits in addition to the original RXTO and RXTO enable bits,
to allow serial rx to function on A7-A9 SoCs. This change does not
appear to affect the A10 SoC and up.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/tty/serial/samsung_tty.c | 17 ++++++++++++-----
include/linux/serial_s3c.h | 18 +++++++++++-------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index 3fdec06322ac..0d184ee2f9ce 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -550,6 +550,7 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
case TYPE_APPLE_S5L:
s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
+ s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
break;
default:
disable_irq_nosync(ourport->rx_irq);
@@ -963,9 +964,11 @@ static irqreturn_t apple_serial_handle_irq(int irq, void *id)
u32 pend = rd_regl(port, S3C2410_UTRSTAT);
irqreturn_t ret = IRQ_NONE;
- if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
+ if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
+ APPLE_S5L_UTRSTAT_RXTO_LEGACY)) {
wr_regl(port, S3C2410_UTRSTAT,
- APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
+ APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
+ APPLE_S5L_UTRSTAT_RXTO_LEGACY);
ret = s3c24xx_serial_rx_irq(ourport);
}
if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
@@ -1190,7 +1193,8 @@ static void apple_s5l_serial_shutdown(struct uart_port *port)
ucon = rd_regl(port, S3C2410_UCON);
ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
- APPLE_S5L_UCON_RXTO_ENA_MSK);
+ APPLE_S5L_UCON_RXTO_ENA_MSK |
+ APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
wr_regl(port, S3C2410_UCON, ucon);
wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
@@ -1287,6 +1291,7 @@ static int apple_s5l_serial_startup(struct uart_port *port)
/* Enable Rx Interrupt */
s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
+ s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
return ret;
}
@@ -2143,13 +2148,15 @@ static int s3c24xx_serial_resume_noirq(struct device *dev)
ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
- APPLE_S5L_UCON_RXTO_ENA_MSK);
+ APPLE_S5L_UCON_RXTO_ENA_MSK |
+ APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
if (ourport->tx_enabled)
ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
if (ourport->rx_enabled)
ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
- APPLE_S5L_UCON_RXTO_ENA_MSK;
+ APPLE_S5L_UCON_RXTO_ENA_MSK |
+ APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK;
wr_regl(port, S3C2410_UCON, ucon);
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
index 1e8686695487..964a4fbf2626 100644
--- a/include/linux/serial_s3c.h
+++ b/include/linux/serial_s3c.h
@@ -246,24 +246,28 @@
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
-#define APPLE_S5L_UCON_RXTO_ENA 9
-#define APPLE_S5L_UCON_RXTHRESH_ENA 12
-#define APPLE_S5L_UCON_TXTHRESH_ENA 13
-#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA)
-#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA)
-#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA)
+#define APPLE_S5L_UCON_RXTO_ENA 9
+#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11
+#define APPLE_S5L_UCON_RXTHRESH_ENA 12
+#define APPLE_S5L_UCON_TXTHRESH_ENA 13
+#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA)
+#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA)
+#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA)
+#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA)
#define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI)
#define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \
+ APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \
APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \
APPLE_S5L_UCON_TXTHRESH_ENA_MSK)
+#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3)
#define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4)
#define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5)
#define APPLE_S5L_UTRSTAT_RXTO BIT(9)
-#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0)
+#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8)
#ifndef __ASSEMBLY__
--
2.46.0Hi Nick, > +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) > #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) > #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) > #define APPLE_S5L_UTRSTAT_RXTO BIT(9) > -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) > +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) As you are here, you could use genmask GENMASK(0xff, 3) Andi
On Tue, Sep 10, 2024 at 02:41:31PM GMT, Andi Shyti wrote: > > +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) > > #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) > > #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) > > #define APPLE_S5L_UTRSTAT_RXTO BIT(9) > > -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) > > +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) > > As you are here, you could use genmask > > GENMASK(0xff, 3) GENMASK(..., 2), of course :-) Andi
On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: > Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is > enabled by bit 11 in UCON. > > Access these bits in addition to the original RXTO and RXTO enable bits, > to allow serial rx to function on A7-A9 SoCs. This change does not > appear to affect the A10 SoC and up. > > Signed-off-by: Nick Chan <towinchenmi@gmail.com> > [snip] > diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h > index 1e8686695487..964a4fbf2626 100644 > --- a/include/linux/serial_s3c.h > +++ b/include/linux/serial_s3c.h > @@ -246,24 +246,28 @@ > S5PV210_UFCON_TXTRIG4 | \ > S5PV210_UFCON_RXTRIG4) > > -#define APPLE_S5L_UCON_RXTO_ENA 9 > -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > +#define APPLE_S5L_UCON_RXTO_ENA 9 > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 > +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) > +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) Small thing, but other diff is not needed except APPLE_S5L_UCON_RXTO_LEGACY_ENA. Kwang. > > #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ > S3C2410_UCON_RXIRQMODE | \ > S3C2410_UCON_RXFIFO_TOI) > #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ > + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ > APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ > APPLE_S5L_UCON_TXTHRESH_ENA_MSK) > > +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) > #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) > #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) > #define APPLE_S5L_UTRSTAT_RXTO BIT(9) > -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) > +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) > > #ifndef __ASSEMBLY__ >
On 9/9/2024 17:43, Kwanghoon Son wrote: > On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: >> Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is >> enabled by bit 11 in UCON. >> >> Access these bits in addition to the original RXTO and RXTO enable bits, >> to allow serial rx to function on A7-A9 SoCs. This change does not >> appear to affect the A10 SoC and up. >> >> Signed-off-by: Nick Chan <towinchenmi@gmail.com> >> > > [snip] > >> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h >> index 1e8686695487..964a4fbf2626 100644 >> --- a/include/linux/serial_s3c.h >> +++ b/include/linux/serial_s3c.h >> @@ -246,24 +246,28 @@ >> S5PV210_UFCON_TXTRIG4 | \ >> S5PV210_UFCON_RXTRIG4) >> >> -#define APPLE_S5L_UCON_RXTO_ENA 9 >> -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >> -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >> -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >> -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >> -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) >> +#define APPLE_S5L_UCON_RXTO_ENA 9 >> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 >> +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >> +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >> +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) >> +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >> +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > Small thing, but other diff is not needed except > APPLE_S5L_UCON_RXTO_LEGACY_ENA. > > Kwang. The other diffs are there to keep everything aligned, it looks like a jumbled mess here in the email, but in an editor like nano it is all aligned, before or after this series. > >> >> #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ >> S3C2410_UCON_RXIRQMODE | \ >> S3C2410_UCON_RXFIFO_TOI) >> #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ >> + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ >> APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ >> APPLE_S5L_UCON_TXTHRESH_ENA_MSK) >> >> +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) >> #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) >> #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) >> #define APPLE_S5L_UTRSTAT_RXTO BIT(9) >> -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) >> +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) >> >> #ifndef __ASSEMBLY__ >> > Nick Chan
On Mon, 2024-09-09 at 17:51 +0800, Nick Chan wrote: > > On 9/9/2024 17:43, Kwanghoon Son wrote: > > On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: > > > Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is > > > enabled by bit 11 in UCON. > > > > > > Access these bits in addition to the original RXTO and RXTO enable bits, > > > to allow serial rx to function on A7-A9 SoCs. This change does not > > > appear to affect the A10 SoC and up. > > > > > > Signed-off-by: Nick Chan <towinchenmi@gmail.com> > > > > > > > [snip] > > > > > diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h > > > index 1e8686695487..964a4fbf2626 100644 > > > --- a/include/linux/serial_s3c.h > > > +++ b/include/linux/serial_s3c.h > > > @@ -246,24 +246,28 @@ > > > S5PV210_UFCON_TXTRIG4 | \ > > > S5PV210_UFCON_RXTRIG4) > > > > > > -#define APPLE_S5L_UCON_RXTO_ENA 9 > > > -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > > > -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > > > -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > > > -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > > > -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > > +#define APPLE_S5L_UCON_RXTO_ENA 9 > > > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 > > > +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > > > +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > > > +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > > > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) > > > +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > > > +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > > > Small thing, but other diff is not needed except > > APPLE_S5L_UCON_RXTO_LEGACY_ENA. > > > > Kwang. > The other diffs are there to keep everything aligned, it looks like a > jumbled mess here in the email, but in an editor like nano it is all > aligned, before or after this series. I know why you did. But still there is way keep aligned and only one line added. you just added one more tab to other lines. If one tab with APPLE_S5L_UCON_RXTO_LEGACY_ENA, then everything will fine. I think less changes better when see git show or blame. Best regards, Kwang. > > > > > > > > > #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ > > > S3C2410_UCON_RXIRQMODE | \ > > > S3C2410_UCON_RXFIFO_TOI) > > > #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ > > > + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ > > > APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ > > > APPLE_S5L_UCON_TXTHRESH_ENA_MSK) > > > > > > +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) > > > #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) > > > #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) > > > #define APPLE_S5L_UTRSTAT_RXTO BIT(9) > > > -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) > > > +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) > > > > > > #ifndef __ASSEMBLY__ > > > > > > > Nick Chan
On 10/9/2024 09:59, Kwanghoon Son wrote: > On Mon, 2024-09-09 at 17:51 +0800, Nick Chan wrote: >> >> On 9/9/2024 17:43, Kwanghoon Son wrote: >>> On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: >>>> Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is >>>> enabled by bit 11 in UCON. >>>> >>>> Access these bits in addition to the original RXTO and RXTO enable bits, >>>> to allow serial rx to function on A7-A9 SoCs. This change does not >>>> appear to affect the A10 SoC and up. >>>> >>>> Signed-off-by: Nick Chan <towinchenmi@gmail.com> >>>> >>> >>> [snip] >>> >>>> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h >>>> index 1e8686695487..964a4fbf2626 100644 >>>> --- a/include/linux/serial_s3c.h >>>> +++ b/include/linux/serial_s3c.h >>>> @@ -246,24 +246,28 @@ >>>> S5PV210_UFCON_TXTRIG4 | \ >>>> S5PV210_UFCON_RXTRIG4) >>>> >>>> -#define APPLE_S5L_UCON_RXTO_ENA 9 >>>> -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >>>> -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >>>> -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >>>> -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >>>> -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) >>>> +#define APPLE_S5L_UCON_RXTO_ENA 9 >>>> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 >>>> +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 >>>> +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 >>>> +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) >>>> +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) >>>> +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) >>>> +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) >>> >>> Small thing, but other diff is not needed except >>> APPLE_S5L_UCON_RXTO_LEGACY_ENA. >>> >>> Kwang. >> The other diffs are there to keep everything aligned, it looks like a >> jumbled mess here in the email, but in an editor like nano it is all >> aligned, before or after this series. > > I know why you did. But still there is way keep aligned and only one > line added. > > you just added one more tab to other lines. > If one tab with APPLE_S5L_UCON_RXTO_LEGACY_ENA, then everything will > fine. > > I think less changes better when see git show or blame. While as you said, APPLE_S5L_UCON_RXTO_LEGACY_ENA would be fine, APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK is too long for that to be aligned, see below without +, - or > distorting everything. Before: #define APPLE_S5L_UCON_RXTO_ENA 9 #define APPLE_S5L_UCON_RXTHRESH_ENA 12 #define APPLE_S5L_UCON_TXTHRESH_ENA 13 #define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA) #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA) #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA) Patch 1: #define APPLE_S5L_UCON_RXTO_ENA 9 #define APPLE_S5L_UCON_RXTHRESH_ENA 12 #define APPLE_S5L_UCON_TXTHRESH_ENA 13 #define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) After: #define APPLE_S5L_UCON_RXTO_ENA 9 #define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 #define APPLE_S5L_UCON_RXTHRESH_ENA 12 #define APPLE_S5L_UCON_TXTHRESH_ENA 13 #define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) #define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > Best regards, > Kwang. > >> >>> >>>> >>>> #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ >>>> S3C2410_UCON_RXIRQMODE | \ >>>> S3C2410_UCON_RXFIFO_TOI) >>>> #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ >>>> + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ >>>> APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ >>>> APPLE_S5L_UCON_TXTHRESH_ENA_MSK) >>>> >>>> +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) >>>> #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) >>>> #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) >>>> #define APPLE_S5L_UTRSTAT_RXTO BIT(9) >>>> -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) >>>> +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) >>>> >>>> #ifndef __ASSEMBLY__ >>>> >>> >> >> Nick Chan > Nick Chan
On Tue, 2024-09-10 at 10:59 +0800, Nick Chan wrote: > > On 10/9/2024 09:59, Kwanghoon Son wrote: > > On Mon, 2024-09-09 at 17:51 +0800, Nick Chan wrote: > > > > > > On 9/9/2024 17:43, Kwanghoon Son wrote: > > > > On Mon, 2024-09-09 at 16:37 +0800, Nick Chan wrote: > > > > > Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is > > > > > enabled by bit 11 in UCON. > > > > > > > > > > Access these bits in addition to the original RXTO and RXTO enable bits, > > > > > to allow serial rx to function on A7-A9 SoCs. This change does not > > > > > appear to affect the A10 SoC and up. > > > > > > > > > > Signed-off-by: Nick Chan <towinchenmi@gmail.com> > > > > > > > > > > > > > [snip] > > > > > > > > > diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h > > > > > index 1e8686695487..964a4fbf2626 100644 > > > > > --- a/include/linux/serial_s3c.h > > > > > +++ b/include/linux/serial_s3c.h > > > > > @@ -246,24 +246,28 @@ > > > > > S5PV210_UFCON_TXTRIG4 | \ > > > > > S5PV210_UFCON_RXTRIG4) > > > > > > > > > > -#define APPLE_S5L_UCON_RXTO_ENA 9 > > > > > -#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > > > > > -#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > > > > > -#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > > > > > -#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > > > > > -#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > > > > +#define APPLE_S5L_UCON_RXTO_ENA 9 > > > > > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 > > > > > +#define APPLE_S5L_UCON_RXTHRESH_ENA 12 > > > > > +#define APPLE_S5L_UCON_TXTHRESH_ENA 13 > > > > > +#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > > > > > +#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) > > > > > +#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > > > > > +#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > > > > > > > Small thing, but other diff is not needed except > > > > APPLE_S5L_UCON_RXTO_LEGACY_ENA. > > > > > > > > Kwang. > > > The other diffs are there to keep everything aligned, it looks like a > > > jumbled mess here in the email, but in an editor like nano it is all > > > aligned, before or after this series. > > > > I know why you did. But still there is way keep aligned and only one > > line added. > > > > you just added one more tab to other lines. > > If one tab with APPLE_S5L_UCON_RXTO_LEGACY_ENA, then everything will > > fine. > > > > I think less changes better when see git show or blame. > While as you said, APPLE_S5L_UCON_RXTO_LEGACY_ENA would be fine, > APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK is too long for that to be aligned, see > below without +, - or > distorting everything. > > Before: > #define APPLE_S5L_UCON_RXTO_ENA 9 > #define APPLE_S5L_UCON_RXTHRESH_ENA 12 > #define APPLE_S5L_UCON_TXTHRESH_ENA 13 > #define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA) > #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA) > #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA) > > Patch 1: > #define APPLE_S5L_UCON_RXTO_ENA 9 > #define APPLE_S5L_UCON_RXTHRESH_ENA 12 > #define APPLE_S5L_UCON_TXTHRESH_ENA 13 > #define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > > After: > #define APPLE_S5L_UCON_RXTO_ENA 9 > #define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11 > #define APPLE_S5L_UCON_RXTHRESH_ENA 12 > #define APPLE_S5L_UCON_TXTHRESH_ENA 13 > #define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA) > #define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK > BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA) > #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA) > #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA) > Okay I got it. Thanks for check! Kwang. > > > > Best regards, > > Kwang. > > > > > > > > > > > > > > > > > > > #define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \ > > > > > S3C2410_UCON_RXIRQMODE | \ > > > > > S3C2410_UCON_RXFIFO_TOI) > > > > > #define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \ > > > > > + APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \ > > > > > APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \ > > > > > APPLE_S5L_UCON_TXTHRESH_ENA_MSK) > > > > > > > > > > +#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) > > > > > #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) > > > > > #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) > > > > > #define APPLE_S5L_UTRSTAT_RXTO BIT(9) > > > > > -#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0) > > > > > +#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8) > > > > > > > > > > #ifndef __ASSEMBLY__ > > > > > > > > > > > > > > > Nick Chan > > > > Nick Chan >
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