On Sun, Sep 08, 2024 at 03:50:47PM +0800, Nick Chan wrote:
> Hi,
>
> This series fixes issues with serial on A7-A11 SoCs. The changes do not
> seem to affect existing M1 and up users so they can be applied
> unconditionally.
>
> Firstly, these SoCs require 32-bit writes on the serial port. This only
> manifested in earlycon as reg-io-width in device tree is consulted for
> normal serial writes.
>
> Secondly, A7-A9 SoCs seems to use different bits for RXTO and RXTO
> enable. Accessing these bits in addition to the original RXTO and RXTO
> enable bits will allow serial rx to work correctly on those SoCs.
>
> Changes in v2:
> - Mention A7-A11 in the comment about changing register accesses to
> MMIO32.
>
> - Use BIT() macro for new entries, and change the existing APPLE_S5L_*
> entries for consistency.
Your subject line does not say "v2" :(
Can you resend this as a v3?
thanks,
greg k-h