Documentation/admin-guide/kernel-parameters.txt | 2 ++ drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 4 ++++ drivers/iommu/amd/init.c | 5 +++++ drivers/iommu/amd/io_pgtable.c | 2 +- 5 files changed, 13 insertions(+), 1 deletion(-)
From: Joerg Roedel <jroedel@suse.de>
Add the 'pgsize_4k' as a valid value to the amd_iommu= command line
parameter to limit the page-sizes used for V1 page-tables for 4 KiB.
This is needed to make some devices working when attached to an AMD
SEV-SNP virtual machine.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
Documentation/admin-guide/kernel-parameters.txt | 2 ++
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/amd_iommu_types.h | 4 ++++
drivers/iommu/amd/init.c | 5 +++++
drivers/iommu/amd/io_pgtable.c | 2 +-
5 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 09126bb8cc9f..3187976ae052 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -339,6 +339,8 @@
pgtbl_v1 - Use v1 page table for DMA-API (Default).
pgtbl_v2 - Use v2 page table for DMA-API.
irtcachedis - Disable Interrupt Remapping Table (IRT) caching.
+ pgsize_4k - Limit the available page-sizes for v1 page-tables
+ to 4 KiB.
amd_iommu_dump= [HW,X86-64]
Enable AMD IOMMU driver option to dump the ACPI table
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 29e6e71f7f9a..6386fa4556d9 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -43,6 +43,7 @@ int amd_iommu_enable_faulting(unsigned int cpu);
extern int amd_iommu_guest_ir;
extern enum io_pgtable_fmt amd_iommu_pgtable;
extern int amd_iommu_gpt_level;
+extern unsigned long amd_iommu_pgsize_bitmap;
/* Protection domain ops */
struct protection_domain *protection_domain_alloc(unsigned int type, int nid);
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 35aa4ff020f5..601fb4ee6900 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -293,6 +293,10 @@
* Page sizes >= the 52 bit max physical address of the CPU are not supported.
*/
#define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G)
+
+/* Special mode where page-sizes are limited to 4 KiB */
+#define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE)
+
/* 4K, 2MB, 1G page sizes are supported */
#define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 6b15ce09e78d..63439f8f0a72 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -192,6 +192,8 @@ bool amdr_ivrs_remap_support __read_mostly;
bool amd_iommu_force_isolation __read_mostly;
+unsigned long amd_iommu_pgsize_bitmap __ro_after_init = AMD_IOMMU_PGSIZES;
+
/*
* AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
* to know which ones are already in use.
@@ -3492,6 +3494,9 @@ static int __init parse_amd_iommu_options(char *str)
amd_iommu_pgtable = AMD_IOMMU_V2;
} else if (strncmp(str, "irtcachedis", 11) == 0) {
amd_iommu_irtcachedis = true;
+ } else if (strncmp(str, "pgsize_4k", 9) == 0) {
+ pr_info("Restricting V1 page-sizes to 4KiB");
+ amd_iommu_pgsize_bitmap = AMD_IOMMU_PGSIZES_4K;
} else {
pr_notice("Unknown option - '%s'\n", str);
}
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c
index 14f62c420e4a..804b788f3f16 100644
--- a/drivers/iommu/amd/io_pgtable.c
+++ b/drivers/iommu/amd/io_pgtable.c
@@ -548,7 +548,7 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
return NULL;
pgtable->mode = PAGE_MODE_3_LEVEL;
- cfg->pgsize_bitmap = AMD_IOMMU_PGSIZES;
+ cfg->pgsize_bitmap = amd_iommu_pgsize_bitmap;
cfg->ias = IOMMU_IN_ADDR_BIT_SIZE;
cfg->oas = IOMMU_OUT_ADDR_BIT_SIZE;
--
2.46.0On Wed, Sep 04, 2024 at 02:59:46PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel@suse.de> > > Add the 'pgsize_4k' as a valid value to the amd_iommu= command line > parameter to limit the page-sizes used for V1 page-tables for 4 KiB. > This is needed to make some devices working when attached to an AMD > SEV-SNP virtual machine. Details? > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > Documentation/admin-guide/kernel-parameters.txt | 2 ++ > drivers/iommu/amd/amd_iommu.h | 1 + > drivers/iommu/amd/amd_iommu_types.h | 4 ++++ > drivers/iommu/amd/init.c | 5 +++++ > drivers/iommu/amd/io_pgtable.c | 2 +- > 5 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 09126bb8cc9f..3187976ae052 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -339,6 +339,8 @@ > pgtbl_v1 - Use v1 page table for DMA-API (Default). > pgtbl_v2 - Use v2 page table for DMA-API. > irtcachedis - Disable Interrupt Remapping Table (IRT) caching. > + pgsize_4k - Limit the available page-sizes for v1 page-tables > + to 4 KiB. Why is this a kernel command line? Surely it should be negotiated automaticaly with capability registers or ACPI like everone else does if there is something functionally wrong with the vIOMMU?? If we are doing this we also have a problem on mlx5 devices where there are too many page sizes in the v1 table and it blows up the ATS caching. It would be nice to widen this option to limit the page sizes to other combinations (4k/2M/1G or something). Jason
On Wed, Sep 04, 2024 at 10:03:29AM -0300, Jason Gunthorpe wrote: > Why is this a kernel command line? Surely it should be negotiated > automaticaly with capability registers or ACPI like everone else does > if there is something functionally wrong with the vIOMMU?? In the affected setups there is no vIOMMU. This is not about secure-IO, the assigned devices will not be part of the trusted base. > If we are doing this we also have a problem on mlx5 devices where > there are too many page sizes in the v1 table and it blows up the ATS > caching. It would be nice to widen this option to limit the page sizes > to other combinations (4k/2M/1G or something). Okay, I will update the patch to allow more settings. Regards, Joerg
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