From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
'link_gen' field is now holding the maximum supported link speed set either
by the controller driver or by DT through 'max-link-speed' property.
But the name 'link_gen' sounds like the negotiated link speed of the PCIe
link. So let's rename it to 'max_link_speed' to make it clear that it holds
the maximum supported link speed of the controller.
NOTE: For the sake of clarity, I've used 'max_link_speed' instead of
'max_link_gen'. Also the link speed and link generation values map 1:1.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pci-imx6.c | 8 ++++----
drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++------
drivers/pci/controller/dwc/pcie-designware.h | 2 +-
drivers/pci/controller/dwc/pcie-intel-gw.c | 4 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +++---
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 964d67756eb2..ef12a4f31740 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -847,12 +847,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
if (ret)
goto err_reset_phy;
- if (pci->link_gen > 1) {
+ if (pci->max_link_speed > 1) {
/* Allow faster modes after the link is up */
dw_pcie_dbi_ro_wr_en(pci);
tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
tmp &= ~PCI_EXP_LNKCAP_SLS;
- tmp |= pci->link_gen;
+ tmp |= pci->max_link_speed;
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
/*
@@ -1386,8 +1386,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
imx6_pcie->tx_swing_low = 127;
/* Limit link speed */
- pci->link_gen = 1;
- of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
+ pci->max_link_speed = 1;
+ of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
if (IS_ERR(imx6_pcie->vpcie)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 1b5aba1f0c92..86c49ba097c6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -166,8 +166,8 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
return ret;
}
- if (pci->link_gen < 1)
- pci->link_gen = of_pci_get_max_link_speed(np);
+ if (pci->max_link_speed < 1)
+ pci->max_link_speed = of_pci_get_max_link_speed(np);
of_property_read_u32(np, "num-lanes", &pci->num_lanes);
@@ -687,7 +687,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci)
}
EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
-static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
+static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 max_link_speed)
{
u32 cap, ctrl2, link_speed;
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -696,7 +696,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
- switch (pcie_link_speed[link_gen]) {
+ switch (pcie_link_speed[max_link_speed]) {
case PCIE_SPEED_2_5GT:
link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
break;
@@ -1058,8 +1058,8 @@ void dw_pcie_setup(struct dw_pcie *pci)
{
u32 val;
- if (pci->link_gen > 0)
- dw_pcie_link_set_max_speed(pci, pci->link_gen);
+ if (pci->max_link_speed > 0)
+ dw_pcie_link_set_max_speed(pci, pci->max_link_speed);
/* Configure Gen1 N_FTS */
if (pci->n_fts[0]) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 53c4c8f399c8..22765564f301 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -421,7 +421,7 @@ struct dw_pcie {
u32 type;
unsigned long caps;
int num_lanes;
- int link_gen;
+ int max_link_speed;
u8 n_fts[2];
struct dw_edma_chip edma;
struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index acbe4f6d3291..676d2aba4fbd 100644
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -132,7 +132,7 @@ static void intel_pcie_link_setup(struct intel_pcie *pcie)
static void intel_pcie_init_n_fts(struct dw_pcie *pci)
{
- switch (pci->link_gen) {
+ switch (pci->max_link_speed) {
case 3:
pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
break;
@@ -252,7 +252,7 @@ static int intel_pcie_wait_l2(struct intel_pcie *pcie)
int ret;
struct dw_pcie *pci = &pcie->pci;
- if (pci->link_gen < 3)
+ if (pci->max_link_speed < 3)
return 0;
/* Send PME_TURN_OFF message */
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index f0f3ebd1a033..00ad4832f2cf 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -141,10 +141,10 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
}
/*
- * Require direct speed change with retrying here if the link_gen is
- * PCIe Gen2 or higher.
+ * Require direct speed change with retrying here if the max_link_speed
+ * is PCIe Gen2 or higher.
*/
- changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
+ changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;
/*
* Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
--
2.25.1Hi Manivannan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 47ac09b91befbb6a235ab620c32af719f8208399]
url: https://github.com/intel-lab-lkp/linux/commits/Manivannan-Sadhasivam-via-B4-Relay/PCI-dwc-Rename-dw_pcie-link_gen-to-dw_pcie-max_link_speed/20240904-151354
base: 47ac09b91befbb6a235ab620c32af719f8208399
patch link: https://lore.kernel.org/r/20240904-pci-qcom-gen4-stability-v6-1-ec39f7ae3f62%40linaro.org
patch subject: [PATCH v6 1/4] PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240906/202409060041.zY2BEBq7-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240906/202409060041.zY2BEBq7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409060041.zY2BEBq7-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-spear13xx.c:236:8: error: no member named 'link_gen' in 'struct dw_pcie'
236 | pci->link_gen = 1;
| ~~~ ^
1 error generated.
vim +236 drivers/pci/controller/dwc/pcie-spear13xx.c
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 190
a43f32d6472730 drivers/pci/host/pcie-spear13xx.c Matwey V. Kornilov 2015-02-19 191 static int spear13xx_pcie_probe(struct platform_device *pdev)
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 192 {
6a43a425a074af drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 193 struct device *dev = &pdev->dev;
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 194 struct dw_pcie *pci;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 195 struct spear13xx_pcie *spear13xx_pcie;
6a43a425a074af drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 196 struct device_node *np = dev->of_node;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 197 int ret;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 198
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 199 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
20f9ece101d879 drivers/pci/host/pcie-spear13xx.c Jingoo Han 2014-11-12 200 if (!spear13xx_pcie)
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 201 return -ENOMEM;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 202
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 203 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 204 if (!pci)
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 205 return -ENOMEM;
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 206
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 207 pci->dev = dev;
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 208 pci->ops = &dw_pcie_ops;
442ec4c04d1235 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 209
c0464062bfea9c drivers/pci/dwc/pcie-spear13xx.c Guenter Roeck 2017-02-25 210 spear13xx_pcie->pci = pci;
c0464062bfea9c drivers/pci/dwc/pcie-spear13xx.c Guenter Roeck 2017-02-25 211
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 212 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 213 if (IS_ERR(spear13xx_pcie->phy)) {
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 214 ret = PTR_ERR(spear13xx_pcie->phy);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 215 if (ret == -EPROBE_DEFER)
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 216 dev_info(dev, "probe deferred\n");
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 217 else
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 218 dev_err(dev, "couldn't get pcie-phy\n");
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 219 return ret;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 220 }
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 221
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 222 phy_init(spear13xx_pcie->phy);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 223
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 224 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 225 if (IS_ERR(spear13xx_pcie->clk)) {
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 226 dev_err(dev, "couldn't get clk for pcie\n");
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 227 return PTR_ERR(spear13xx_pcie->clk);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 228 }
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 229 ret = clk_prepare_enable(spear13xx_pcie->clk);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 230 if (ret) {
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 231 dev_err(dev, "couldn't enable clk for pcie\n");
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 232 return ret;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 233 }
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 234
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 235 if (of_property_read_bool(np, "st,pcie-is-gen1"))
39bc5006501cc3 drivers/pci/controller/dwc/pcie-spear13xx.c Rob Herring 2020-08-20 @236 pci->link_gen = 1;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 237
9bcf0a6fdc5062 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 238 platform_set_drvdata(pdev, spear13xx_pcie);
9bcf0a6fdc5062 drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 239
ffe82fa66afb19 drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 240 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 241 if (ret < 0)
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 242 goto fail_clk;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 243
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 244 return 0;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 245
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 246 fail_clk:
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 247 clk_disable_unprepare(spear13xx_pcie->clk);
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 248
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 249 return ret;
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 250 }
51b66a6ce12570 drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 251
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Manivannan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 47ac09b91befbb6a235ab620c32af719f8208399]
url: https://github.com/intel-lab-lkp/linux/commits/Manivannan-Sadhasivam-via-B4-Relay/PCI-dwc-Rename-dw_pcie-link_gen-to-dw_pcie-max_link_speed/20240904-151354
base: 47ac09b91befbb6a235ab620c32af719f8208399
patch link: https://lore.kernel.org/r/20240904-pci-qcom-gen4-stability-v6-1-ec39f7ae3f62%40linaro.org
patch subject: [PATCH v6 1/4] PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
config: arc-allmodconfig (https://download.01.org/0day-ci/archive/20240905/202409051650.UA8WoHFz-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240905/202409051650.UA8WoHFz-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409051650.UA8WoHFz-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-spear13xx.c: In function 'spear13xx_pcie_probe':
>> drivers/pci/controller/dwc/pcie-spear13xx.c:236:20: error: 'struct dw_pcie' has no member named 'link_gen'
236 | pci->link_gen = 1;
| ^~
vim +236 drivers/pci/controller/dwc/pcie-spear13xx.c
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 190
a43f32d64727302 drivers/pci/host/pcie-spear13xx.c Matwey V. Kornilov 2015-02-19 191 static int spear13xx_pcie_probe(struct platform_device *pdev)
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 192 {
6a43a425a074afc drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 193 struct device *dev = &pdev->dev;
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 194 struct dw_pcie *pci;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 195 struct spear13xx_pcie *spear13xx_pcie;
6a43a425a074afc drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 196 struct device_node *np = dev->of_node;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 197 int ret;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 198
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 199 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
20f9ece101d8793 drivers/pci/host/pcie-spear13xx.c Jingoo Han 2014-11-12 200 if (!spear13xx_pcie)
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 201 return -ENOMEM;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 202
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 203 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 204 if (!pci)
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 205 return -ENOMEM;
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 206
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 207 pci->dev = dev;
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 208 pci->ops = &dw_pcie_ops;
442ec4c04d1235f drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 209
c0464062bfea9cd drivers/pci/dwc/pcie-spear13xx.c Guenter Roeck 2017-02-25 210 spear13xx_pcie->pci = pci;
c0464062bfea9cd drivers/pci/dwc/pcie-spear13xx.c Guenter Roeck 2017-02-25 211
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 212 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 213 if (IS_ERR(spear13xx_pcie->phy)) {
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 214 ret = PTR_ERR(spear13xx_pcie->phy);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 215 if (ret == -EPROBE_DEFER)
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 216 dev_info(dev, "probe deferred\n");
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 217 else
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 218 dev_err(dev, "couldn't get pcie-phy\n");
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 219 return ret;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 220 }
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 221
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 222 phy_init(spear13xx_pcie->phy);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 223
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 224 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 225 if (IS_ERR(spear13xx_pcie->clk)) {
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 226 dev_err(dev, "couldn't get clk for pcie\n");
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 227 return PTR_ERR(spear13xx_pcie->clk);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 228 }
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 229 ret = clk_prepare_enable(spear13xx_pcie->clk);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 230 if (ret) {
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 231 dev_err(dev, "couldn't enable clk for pcie\n");
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 232 return ret;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 233 }
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 234
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 235 if (of_property_read_bool(np, "st,pcie-is-gen1"))
39bc5006501cc31 drivers/pci/controller/dwc/pcie-spear13xx.c Rob Herring 2020-08-20 @236 pci->link_gen = 1;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 237
9bcf0a6fdc5062e drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 238 platform_set_drvdata(pdev, spear13xx_pcie);
9bcf0a6fdc5062e drivers/pci/dwc/pcie-spear13xx.c Kishon Vijay Abraham I 2017-02-15 239
ffe82fa66afb19c drivers/pci/host/pcie-spear13xx.c Bjorn Helgaas 2016-10-06 240 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 241 if (ret < 0)
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 242 goto fail_clk;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 243
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 244 return 0;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 245
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 246 fail_clk:
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 247 clk_disable_unprepare(spear13xx_pcie->clk);
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 248
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 249 return ret;
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 250 }
51b66a6ce12570e drivers/pci/host/pcie-spear13xx.c Pratyush Anand 2014-02-11 251
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Wed, Sep 04, 2024 at 12:41:57PM +0530, Manivannan Sadhasivam wrote:
> 'link_gen' field is now holding the maximum supported link speed set either
> by the controller driver or by DT through 'max-link-speed' property.
>
> But the name 'link_gen' sounds like the negotiated link speed of the PCIe
> link. So let's rename it to 'max_link_speed' to make it clear that it holds
> the maximum supported link speed of the controller.
>
> NOTE: For the sake of clarity, I've used 'max_link_speed' instead of
> 'max_link_gen'. Also the link speed and link generation values map 1:1.
Maybe a little confuse is about unit of max_link_speed. the word 'gen'
(1, 2, 3...), we know it PCIe[1,2,3...]. But word "speed" look like should
be some mHz.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 8 ++++----
> drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++------
> drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> drivers/pci/controller/dwc/pcie-intel-gw.c | 4 ++--
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +++---
> 5 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 964d67756eb2..ef12a4f31740 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -847,12 +847,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> if (ret)
> goto err_reset_phy;
>
> - if (pci->link_gen > 1) {
> + if (pci->max_link_speed > 1) {
> /* Allow faster modes after the link is up */
> dw_pcie_dbi_ro_wr_en(pci);
> tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> tmp &= ~PCI_EXP_LNKCAP_SLS;
> - tmp |= pci->link_gen;
> + tmp |= pci->max_link_speed;
> dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
>
> /*
> @@ -1386,8 +1386,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> imx6_pcie->tx_swing_low = 127;
>
> /* Limit link speed */
> - pci->link_gen = 1;
> - of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
> + pci->max_link_speed = 1;
> + of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
>
> imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
> if (IS_ERR(imx6_pcie->vpcie)) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 1b5aba1f0c92..86c49ba097c6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -166,8 +166,8 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
> return ret;
> }
>
> - if (pci->link_gen < 1)
> - pci->link_gen = of_pci_get_max_link_speed(np);
> + if (pci->max_link_speed < 1)
> + pci->max_link_speed = of_pci_get_max_link_speed(np);
>
> of_property_read_u32(np, "num-lanes", &pci->num_lanes);
>
> @@ -687,7 +687,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci)
> }
> EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
>
> -static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> +static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 max_link_speed)
> {
> u32 cap, ctrl2, link_speed;
> u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> @@ -696,7 +696,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
> ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
>
> - switch (pcie_link_speed[link_gen]) {
> + switch (pcie_link_speed[max_link_speed]) {
> case PCIE_SPEED_2_5GT:
> link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
> break;
> @@ -1058,8 +1058,8 @@ void dw_pcie_setup(struct dw_pcie *pci)
> {
> u32 val;
>
> - if (pci->link_gen > 0)
> - dw_pcie_link_set_max_speed(pci, pci->link_gen);
> + if (pci->max_link_speed > 0)
> + dw_pcie_link_set_max_speed(pci, pci->max_link_speed);
>
> /* Configure Gen1 N_FTS */
> if (pci->n_fts[0]) {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 53c4c8f399c8..22765564f301 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -421,7 +421,7 @@ struct dw_pcie {
> u32 type;
> unsigned long caps;
> int num_lanes;
> - int link_gen;
> + int max_link_speed;
> u8 n_fts[2];
> struct dw_edma_chip edma;
> struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
> diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
> index acbe4f6d3291..676d2aba4fbd 100644
> --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
> +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
> @@ -132,7 +132,7 @@ static void intel_pcie_link_setup(struct intel_pcie *pcie)
>
> static void intel_pcie_init_n_fts(struct dw_pcie *pci)
> {
> - switch (pci->link_gen) {
> + switch (pci->max_link_speed) {
> case 3:
> pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
> break;
> @@ -252,7 +252,7 @@ static int intel_pcie_wait_l2(struct intel_pcie *pcie)
> int ret;
> struct dw_pcie *pci = &pcie->pci;
>
> - if (pci->link_gen < 3)
> + if (pci->max_link_speed < 3)
> return 0;
>
> /* Send PME_TURN_OFF message */
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index f0f3ebd1a033..00ad4832f2cf 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -141,10 +141,10 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> }
>
> /*
> - * Require direct speed change with retrying here if the link_gen is
> - * PCIe Gen2 or higher.
> + * Require direct speed change with retrying here if the max_link_speed
> + * is PCIe Gen2 or higher.
> */
> - changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> + changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;
>
> /*
> * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
>
> --
> 2.25.1
>
On Wed, Sep 04, 2024 at 11:58:58AM -0400, Frank Li wrote:
> On Wed, Sep 04, 2024 at 12:41:57PM +0530, Manivannan Sadhasivam wrote:
> > 'link_gen' field is now holding the maximum supported link speed set either
> > by the controller driver or by DT through 'max-link-speed' property.
> >
> > But the name 'link_gen' sounds like the negotiated link speed of the PCIe
> > link. So let's rename it to 'max_link_speed' to make it clear that it holds
> > the maximum supported link speed of the controller.
> >
> > NOTE: For the sake of clarity, I've used 'max_link_speed' instead of
> > 'max_link_gen'. Also the link speed and link generation values map 1:1.
>
> Maybe a little confuse is about unit of max_link_speed. the word 'gen'
> (1, 2, 3...), we know it PCIe[1,2,3...]. But word "speed" look like should
> be some mHz.
>
Ideally, the DT property should've used the definitions in pci.h, but it ended
up accepting the PCIe Gen version. Still, it is named as 'max-link-speed', so I
wanted to keept the same name for the variable.
- Mani
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 8 ++++----
> > drivers/pci/controller/dwc/pcie-designware.c | 12 ++++++------
> > drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> > drivers/pci/controller/dwc/pcie-intel-gw.c | 4 ++--
> > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +++---
> > 5 files changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 964d67756eb2..ef12a4f31740 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -847,12 +847,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> > if (ret)
> > goto err_reset_phy;
> >
> > - if (pci->link_gen > 1) {
> > + if (pci->max_link_speed > 1) {
> > /* Allow faster modes after the link is up */
> > dw_pcie_dbi_ro_wr_en(pci);
> > tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> > tmp &= ~PCI_EXP_LNKCAP_SLS;
> > - tmp |= pci->link_gen;
> > + tmp |= pci->max_link_speed;
> > dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
> >
> > /*
> > @@ -1386,8 +1386,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
> > imx6_pcie->tx_swing_low = 127;
> >
> > /* Limit link speed */
> > - pci->link_gen = 1;
> > - of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
> > + pci->max_link_speed = 1;
> > + of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
> >
> > imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
> > if (IS_ERR(imx6_pcie->vpcie)) {
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 1b5aba1f0c92..86c49ba097c6 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -166,8 +166,8 @@ int dw_pcie_get_resources(struct dw_pcie *pci)
> > return ret;
> > }
> >
> > - if (pci->link_gen < 1)
> > - pci->link_gen = of_pci_get_max_link_speed(np);
> > + if (pci->max_link_speed < 1)
> > + pci->max_link_speed = of_pci_get_max_link_speed(np);
> >
> > of_property_read_u32(np, "num-lanes", &pci->num_lanes);
> >
> > @@ -687,7 +687,7 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci)
> > }
> > EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
> >
> > -static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > +static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 max_link_speed)
> > {
> > u32 cap, ctrl2, link_speed;
> > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > @@ -696,7 +696,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
> > ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
> >
> > - switch (pcie_link_speed[link_gen]) {
> > + switch (pcie_link_speed[max_link_speed]) {
> > case PCIE_SPEED_2_5GT:
> > link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
> > break;
> > @@ -1058,8 +1058,8 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > {
> > u32 val;
> >
> > - if (pci->link_gen > 0)
> > - dw_pcie_link_set_max_speed(pci, pci->link_gen);
> > + if (pci->max_link_speed > 0)
> > + dw_pcie_link_set_max_speed(pci, pci->max_link_speed);
> >
> > /* Configure Gen1 N_FTS */
> > if (pci->n_fts[0]) {
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 53c4c8f399c8..22765564f301 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -421,7 +421,7 @@ struct dw_pcie {
> > u32 type;
> > unsigned long caps;
> > int num_lanes;
> > - int link_gen;
> > + int max_link_speed;
> > u8 n_fts[2];
> > struct dw_edma_chip edma;
> > struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
> > diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
> > index acbe4f6d3291..676d2aba4fbd 100644
> > --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
> > +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
> > @@ -132,7 +132,7 @@ static void intel_pcie_link_setup(struct intel_pcie *pcie)
> >
> > static void intel_pcie_init_n_fts(struct dw_pcie *pci)
> > {
> > - switch (pci->link_gen) {
> > + switch (pci->max_link_speed) {
> > case 3:
> > pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
> > break;
> > @@ -252,7 +252,7 @@ static int intel_pcie_wait_l2(struct intel_pcie *pcie)
> > int ret;
> > struct dw_pcie *pci = &pcie->pci;
> >
> > - if (pci->link_gen < 3)
> > + if (pci->max_link_speed < 3)
> > return 0;
> >
> > /* Send PME_TURN_OFF message */
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > index f0f3ebd1a033..00ad4832f2cf 100644
> > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > @@ -141,10 +141,10 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> > }
> >
> > /*
> > - * Require direct speed change with retrying here if the link_gen is
> > - * PCIe Gen2 or higher.
> > + * Require direct speed change with retrying here if the max_link_speed
> > + * is PCIe Gen2 or higher.
> > */
> > - changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> > + changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;
> >
> > /*
> > * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> >
> > --
> > 2.25.1
> >
--
மணிவண்ணன் சதாசிவம்
On Wed, Sep 04, 2024 at 12:41:57PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > 'link_gen' field is now holding the maximum supported link speed set either > by the controller driver or by DT through 'max-link-speed' property. > > But the name 'link_gen' sounds like the negotiated link speed of the PCIe > link. So let's rename it to 'max_link_speed' to make it clear that it holds > the maximum supported link speed of the controller. > > NOTE: For the sake of clarity, I've used 'max_link_speed' instead of > 'max_link_gen'. Also the link speed and link generation values map 1:1. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
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