From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
[v3] Added reviewed-by tags
.../phy/qcom,ipq5018-uniphy-pcie.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
new file mode 100644
index 000000000000..c04dd179eb8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5018-uniphy-pcie-gen2x1
+ - qcom,ipq5018-uniphy-pcie-gen2x2
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pipe
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ "#phy-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+ phy@86000 {
+ compatible = "qcom,ipq5018-uniphy-pcie-gen2x2";
+ reg = <0x86000 0x1000>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe";
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ };
--
2.34.1On Fri, Aug 30, 2024 at 01:41:27PM +0530, Sricharan R wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > [v3] Added reviewed-by tags > > .../phy/qcom,ipq5018-uniphy-pcie.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml > new file mode 100644 > index 000000000000..c04dd179eb8b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2 > + > +maintainers: > + - Nitheesh Sekar <quic_nsekar@quicinc.com> > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > + > +properties: > + compatible: > + enum: > + - qcom,ipq5018-uniphy-pcie-gen2x1 > + - qcom,ipq5018-uniphy-pcie-gen2x2 ... and now I wonder why there are two compatibles. Isn't the phy the same? We talk about the same hardware? Best regards, Krzysztof
On 8/30/2024 1:53 PM, Krzysztof Kozlowski wrote: > On Fri, Aug 30, 2024 at 01:41:27PM +0530, Sricharan R wrote: >> From: Nitheesh Sekar <quic_nsekar@quicinc.com> >> >> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> [v3] Added reviewed-by tags >> >> .../phy/qcom,ipq5018-uniphy-pcie.yaml | 70 +++++++++++++++++++ >> 1 file changed, 70 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >> new file mode 100644 >> index 000000000000..c04dd179eb8b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >> @@ -0,0 +1,70 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2 >> + >> +maintainers: >> + - Nitheesh Sekar <quic_nsekar@quicinc.com> >> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,ipq5018-uniphy-pcie-gen2x1 >> + - qcom,ipq5018-uniphy-pcie-gen2x2 > > ... and now I wonder why there are two compatibles. Isn't the phy the > same? We talk about the same hardware? We have 2 different physical phys. One with single lane and another with dual lane. Its same IP, but for 2 lanes, 2 sets of the phy specific registers needs to configured. So differentiating that here. Regards, Sricharan
On 04/09/2024 19:20, Sricharan Ramabadhran wrote: > > > On 8/30/2024 1:53 PM, Krzysztof Kozlowski wrote: >> On Fri, Aug 30, 2024 at 01:41:27PM +0530, Sricharan R wrote: >>> From: Nitheesh Sekar <quic_nsekar@quicinc.com> >>> >>> Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018. >>> >>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> --- >>> [v3] Added reviewed-by tags >>> >>> .../phy/qcom,ipq5018-uniphy-pcie.yaml | 70 +++++++++++++++++++ >>> 1 file changed, 70 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >>> new file mode 100644 >>> index 000000000000..c04dd179eb8b >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml >>> @@ -0,0 +1,70 @@ >>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2 >>> + >>> +maintainers: >>> + - Nitheesh Sekar <quic_nsekar@quicinc.com> >>> + - Sricharan Ramabadhran <quic_srichara@quicinc.com> >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - qcom,ipq5018-uniphy-pcie-gen2x1 >>> + - qcom,ipq5018-uniphy-pcie-gen2x2 >> >> ... and now I wonder why there are two compatibles. Isn't the phy the >> same? We talk about the same hardware? > We have 2 different physical phys. One with single lane and another > with dual lane. Its same IP, but for 2 lanes, 2 sets of the phy > specific registers needs to configured. So differentiating that here. What you described, suggests using phy mode or num-lanes in PCI controller, not separate compatible. It's the same IP. Best regards, Krzysztof
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