The PTE bit(9) is reserved for software, now used by DEVMAP,
this patch reuse bit(9) for soft-dirty which is enabled only
if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
and devmap will be mutually exclusive on RISC-V.
To add swap PTE soft-dirty tracking, we borrow bit (4) which is
available for swap PTEs on RISC-V systems.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
arch/riscv/Kconfig | 27 ++++++++++-
arch/riscv/include/asm/pgtable-bits.h | 12 +++++
arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
3 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0f3cd7c3a436..f1460fc01cd4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -39,7 +39,6 @@ config RISCV
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PMEM_API
select ARCH_HAS_PREPARE_SYNC_CORE_CMD
- select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
select ARCH_HAS_PTE_SPECIAL
select ARCH_HAS_SET_DIRECT_MAP if MMU
select ARCH_HAS_SET_MEMORY if MMU
@@ -948,6 +947,32 @@ config RANDOMIZE_BASE
If unsure, say N.
+choice
+ prompt "PET RSW Bit(9) used for"
+ default RISCV_HAS_PTE_DEVMEP
+ depends on MMU && 64BIT
+ help
+ RISC-V PTE bit(9) is reserved for software, and used by more than
+ one kernel features which cannot be supported at the same time.
+ So we have to select one for it.
+
+config RISCV_HAS_PTE_DEVMEP
+ bool "DEVMAP mark"
+ select ARCH_HAS_PTE_DEVMAP
+ help
+ The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
+ PTEs support to function.
+
+ So if you want to use ZONE_DEVICE, select this.
+
+config RISCV_HAS_SOFT_DIRTY
+ bool "soft dirty"
+ select HAVE_ARCH_SOFT_DIRTY
+ help
+ The PTE bit(9) is used for soft-dirty tracking.
+
+endchoice
+
endmenu # "Kernel features"
menu "Boot options"
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 5bcc73430829..c6d51fe9fc6f 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -26,6 +26,18 @@
#define _PAGE_DEVMAP 0
#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
+#ifdef CONFIG_MEM_SOFT_DIRTY
+#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
+/*
+ * BIT 4 is not involved into swap entry computation, so we
+ * can borrow it for swap page soft-dirty tracking.
+ */
+#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
+#else
+#define _PAGE_SOFT_DIRTY 0
+#define _PAGE_SWP_SOFT_DIRTY 0
+#endif /* CONFIG_MEM_SOFT_DIRTY */
+
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 089f3c9f56a3..d41507919ef2 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
static inline pte_t pte_mkdirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_DIRTY);
+ return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
}
static inline pte_t pte_mkclean(pte_t pte)
@@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
return pte;
}
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline int pte_soft_dirty(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SOFT_DIRTY;
+}
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
+}
+
+static inline pte_t pte_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
+}
+
+static inline int pte_swp_soft_dirty(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
+}
+
+static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
+}
+
+static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
+}
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
#ifdef CONFIG_RISCV_ISA_SVNAPOT
#define pte_leaf_size(pte) (pte_napot(pte) ? \
napot_cont_size(napot_cont_order(pte)) :\
@@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
}
+#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
+static inline int pmd_soft_dirty(pmd_t pmd)
+{
+ return pte_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
+}
+
+#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
+static inline int pmd_swp_soft_dirty(pmd_t pmd)
+{
+ return pte_swp_soft_dirty(pmd_pte(pmd));
+}
+
+static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
+}
+
+static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
+{
+ return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
+}
+#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
+#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
+
static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
pmd_t *pmdp, pmd_t pmd)
{
@@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
* Format of swap PTE:
* bit 0: _PAGE_PRESENT (zero)
* bit 1 to 3: _PAGE_LEAF (zero)
+ * bit 4: _PAGE_SWP_SOFT_DIRTY
* bit 5: _PAGE_PROT_NONE (zero)
* bit 6: exclusive marker
* bits 7 to 11: swap type
--
2.34.1On 30/08/2024 03:11, Chunyan Zhang wrote:
> The PTE bit(9) is reserved for software, now used by DEVMAP,
> this patch reuse bit(9) for soft-dirty which is enabled only
s/reuse/reuses
> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> and devmap will be mutually exclusive on RISC-V.
>
> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> available for swap PTEs on RISC-V systems.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 27 ++++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 0f3cd7c3a436..f1460fc01cd4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -39,7 +39,6 @@ config RISCV
> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> select ARCH_HAS_PMEM_API
> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> select ARCH_HAS_PTE_SPECIAL
> select ARCH_HAS_SET_DIRECT_MAP if MMU
> select ARCH_HAS_SET_MEMORY if MMU
> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>
> If unsure, say N.
>
> +choice
> + prompt "PET RSW Bit(9) used for"
I would say: "PTE RSW bit(9) usage"
> + default RISCV_HAS_PTE_DEVMEP
s/DEVMEP/DEVMAP
> + depends on MMU && 64BIT
> + help
> + RISC-V PTE bit(9) is reserved for software, and used by more than
> + one kernel features which cannot be supported at the same time.
s/features/feature
> + So we have to select one for it.
> +
> +config RISCV_HAS_PTE_DEVMEP
> + bool "DEVMAP mark"
I would say simply "devmap"
> + select ARCH_HAS_PTE_DEVMAP
> + help
> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
"is used for devmap...pages need devmap"
> + PTEs support to function.
> +
> + So if you want to use ZONE_DEVICE, select this.
> +
> +config RISCV_HAS_SOFT_DIRTY
> + bool "soft dirty"
s/soft dirty/soft-dirty
> + select HAVE_ARCH_SOFT_DIRTY
> + help
> + The PTE bit(9) is used for soft-dirty tracking.
> +
> +endchoice
> +
> endmenu # "Kernel features"
>
> menu "Boot options"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index 5bcc73430829..c6d51fe9fc6f 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -26,6 +26,18 @@
> #define _PAGE_DEVMAP 0
> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>
> +#ifdef CONFIG_MEM_SOFT_DIRTY
For consistency with CONFIG_ARCH_HAS_PTE_DEVMAP, I would use
CONFIG_HAVE_ARCH_SOFT_DIRTY
> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> +/*
> + * BIT 4 is not involved into swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> +#else
> +#define _PAGE_SOFT_DIRTY 0
> +#define _PAGE_SWP_SOFT_DIRTY 0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
Same here.
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 089f3c9f56a3..d41507919ef2 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> return pte;
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pte_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> +}
> +
> +static inline int pte_swp_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> napot_cont_size(napot_cont_order(pte)) :\
> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pmd_soft_dirty(pmd_t pmd)
> +{
> + return pte_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +
> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> +{
> + return pte_swp_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
Apart from the minor things above, the rest looks good so you can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
On Tue, 5 Nov 2024 at 21:13, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> On 30/08/2024 03:11, Chunyan Zhang wrote:
> > The PTE bit(9) is reserved for software, now used by DEVMAP,
> > this patch reuse bit(9) for soft-dirty which is enabled only
>
>
> s/reuse/reuses
>
>
> > if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> > and devmap will be mutually exclusive on RISC-V.
> >
> > To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> > available for swap PTEs on RISC-V systems.
> >
> > Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> > ---
> > arch/riscv/Kconfig | 27 ++++++++++-
> > arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> > arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> > 3 files changed, 106 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 0f3cd7c3a436..f1460fc01cd4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -39,7 +39,6 @@ config RISCV
> > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > select ARCH_HAS_PMEM_API
> > select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> > - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> > select ARCH_HAS_PTE_SPECIAL
> > select ARCH_HAS_SET_DIRECT_MAP if MMU
> > select ARCH_HAS_SET_MEMORY if MMU
> > @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >
> > If unsure, say N.
> >
> > +choice
> > + prompt "PET RSW Bit(9) used for"
>
>
> I would say: "PTE RSW bit(9) usage"
>
>
> > + default RISCV_HAS_PTE_DEVMEP
>
>
> s/DEVMEP/DEVMAP
>
>
> > + depends on MMU && 64BIT
> > + help
> > + RISC-V PTE bit(9) is reserved for software, and used by more than
> > + one kernel features which cannot be supported at the same time.
>
>
> s/features/feature
>
>
> > + So we have to select one for it.
> > +
> > +config RISCV_HAS_PTE_DEVMEP
> > + bool "DEVMAP mark"
>
>
> I would say simply "devmap"
Ok, only "devmap" without the following "mark", right?
>
>
> > + select ARCH_HAS_PTE_DEVMAP
> > + help
> > + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
>
>
> "is used for devmap...pages need devmap"
>
>
> > + PTEs support to function.
> > +
> > + So if you want to use ZONE_DEVICE, select this.
> > +
> > +config RISCV_HAS_SOFT_DIRTY
> > + bool "soft dirty"
>
>
> s/soft dirty/soft-dirty
>
>
> > + select HAVE_ARCH_SOFT_DIRTY
> > + help
> > + The PTE bit(9) is used for soft-dirty tracking.
> > +
> > +endchoice
> > +
> > endmenu # "Kernel features"
> >
> > menu "Boot options"
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index 5bcc73430829..c6d51fe9fc6f 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -26,6 +26,18 @@
> > #define _PAGE_DEVMAP 0
> > #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >
> > +#ifdef CONFIG_MEM_SOFT_DIRTY
>
>
> For consistency with CONFIG_ARCH_HAS_PTE_DEVMAP, I would use
> CONFIG_HAVE_ARCH_SOFT_DIRTY
CONFIG_MEM_SOFT_DIRTY is not equal to the CONFIG_HAVE_ARCH_SOFT_DIRTY,
the latter is one of its dependencies.
If CONFIG_HAVE_ARCH_SOFT_DIRTY is selected, but CONFIG_MEM_SOFT_DIRTY
is not, the bit(9) should not be set/cleared by pte soft_dirty APIs?
Also considering x86 is using CONFIG_MEM_SOFT_DIRTY here, should we
keep the same?
>
>
> > +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> > +/*
> > + * BIT 4 is not involved into swap entry computation, so we
> > + * can borrow it for swap page soft-dirty tracking.
> > + */
> > +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> > +#else
> > +#define _PAGE_SOFT_DIRTY 0
> > +#define _PAGE_SWP_SOFT_DIRTY 0
> > +#endif /* CONFIG_MEM_SOFT_DIRTY */
>
>
> Same here.
>
>
> > +
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > /*
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 089f3c9f56a3..d41507919ef2 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >
> > static inline pte_t pte_mkdirty(pte_t pte)
> > {
> > - return __pte(pte_val(pte) | _PAGE_DIRTY);
> > + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> > }
> >
> > static inline pte_t pte_mkclean(pte_t pte)
> > @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> > return pte;
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pte_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> > +}
> > +
> > +static inline int pte_swp_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> > +}
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
> > #define pte_leaf_size(pte) (pte_napot(pte) ? \
> > napot_cont_size(napot_cont_order(pte)) :\
> > @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pmd_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> > +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_swp_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> > pmd_t *pmdp, pmd_t pmd)
> > {
> > @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> > * Format of swap PTE:
> > * bit 0: _PAGE_PRESENT (zero)
> > * bit 1 to 3: _PAGE_LEAF (zero)
> > + * bit 4: _PAGE_SWP_SOFT_DIRTY
> > * bit 5: _PAGE_PROT_NONE (zero)
> > * bit 6: exclusive marker
> > * bits 7 to 11: swap type
>
>
> Apart from the minor things above, the rest looks good so you can add:
>
> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks for the review,
Chunyan
On 2024/8/30 9:11, Chunyan Zhang wrote:
> The PTE bit(9) is reserved for software, now used by DEVMAP,
> this patch reuse bit(9) for soft-dirty which is enabled only
> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> and devmap will be mutually exclusive on RISC-V.
>
> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> available for swap PTEs on RISC-V systems.
>
> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> ---
> arch/riscv/Kconfig | 27 ++++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 0f3cd7c3a436..f1460fc01cd4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -39,7 +39,6 @@ config RISCV
> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> select ARCH_HAS_PMEM_API
> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> select ARCH_HAS_PTE_SPECIAL
> select ARCH_HAS_SET_DIRECT_MAP if MMU
> select ARCH_HAS_SET_MEMORY if MMU
> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>
> If unsure, say N.
>
> +choice
> + prompt "PET RSW Bit(9) used for"
> + default RISCV_HAS_PTE_DEVMEP
> + depends on MMU && 64BIT
> + help
> + RISC-V PTE bit(9) is reserved for software, and used by more than
> + one kernel features which cannot be supported at the same time.
> + So we have to select one for it.
> +
> +config RISCV_HAS_PTE_DEVMEP
> + bool "DEVMAP mark"
> + select ARCH_HAS_PTE_DEVMAP
> + help
> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> + PTEs support to function.
> +
> + So if you want to use ZONE_DEVICE, select this.
> +
> +config RISCV_HAS_SOFT_DIRTY
> + bool "soft dirty"
> + select HAVE_ARCH_SOFT_DIRTY
> + help
> + The PTE bit(9) is used for soft-dirty tracking.
> +
> +endchoice
> +
Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
riscv will too:
https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> endmenu # "Kernel features"
>
> menu "Boot options"
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index 5bcc73430829..c6d51fe9fc6f 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -26,6 +26,18 @@
> #define _PAGE_DEVMAP 0
> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>
> +#ifdef CONFIG_MEM_SOFT_DIRTY
> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> +/*
> + * BIT 4 is not involved into swap entry computation, so we
> + * can borrow it for swap page soft-dirty tracking.
> + */
> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> +#else
> +#define _PAGE_SOFT_DIRTY 0
> +#define _PAGE_SWP_SOFT_DIRTY 0
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> +
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 089f3c9f56a3..d41507919ef2 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>
> static inline pte_t pte_mkdirty(pte_t pte)
> {
> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> }
>
> static inline pte_t pte_mkclean(pte_t pte)
> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> return pte;
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pte_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> +}
> +
> +static inline int pte_swp_soft_dirty(pte_t pte)
> +{
> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> napot_cont_size(napot_cont_order(pte)) :\
> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline int pmd_soft_dirty(pmd_t pmd)
> +{
> + return pte_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +
> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> +{
> + return pte_swp_soft_dirty(pmd_pte(pmd));
> +}
> +
> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> +}
> +
> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> +{
> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> +}
> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> * Format of swap PTE:
> * bit 0: _PAGE_PRESENT (zero)
> * bit 1 to 3: _PAGE_LEAF (zero)
> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> * bit 5: _PAGE_PROT_NONE (zero)
> * bit 6: exclusive marker
> * bits 7 to 11: swap type
Hi Jinjie,
On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>
>
>
> On 2024/8/30 9:11, Chunyan Zhang wrote:
> > The PTE bit(9) is reserved for software, now used by DEVMAP,
> > this patch reuse bit(9) for soft-dirty which is enabled only
> > if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> > and devmap will be mutually exclusive on RISC-V.
> >
> > To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> > available for swap PTEs on RISC-V systems.
> >
> > Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> > ---
> > arch/riscv/Kconfig | 27 ++++++++++-
> > arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> > arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> > 3 files changed, 106 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 0f3cd7c3a436..f1460fc01cd4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -39,7 +39,6 @@ config RISCV
> > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > select ARCH_HAS_PMEM_API
> > select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> > - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> > select ARCH_HAS_PTE_SPECIAL
> > select ARCH_HAS_SET_DIRECT_MAP if MMU
> > select ARCH_HAS_SET_MEMORY if MMU
> > @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >
> > If unsure, say N.
> >
> > +choice
> > + prompt "PET RSW Bit(9) used for"
> > + default RISCV_HAS_PTE_DEVMEP
> > + depends on MMU && 64BIT
> > + help
> > + RISC-V PTE bit(9) is reserved for software, and used by more than
> > + one kernel features which cannot be supported at the same time.
> > + So we have to select one for it.
> > +
> > +config RISCV_HAS_PTE_DEVMEP
> > + bool "DEVMAP mark"
> > + select ARCH_HAS_PTE_DEVMAP
> > + help
> > + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> > + PTEs support to function.
> > +
> > + So if you want to use ZONE_DEVICE, select this.
> > +
> > +config RISCV_HAS_SOFT_DIRTY
> > + bool "soft dirty"
> > + select HAVE_ARCH_SOFT_DIRTY
> > + help
> > + The PTE bit(9) is used for soft-dirty tracking.
> > +
> > +endchoice
> > +
>
> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
> riscv will too:
>
> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
Thanks for sharing, I didn't notice this.
It looks like we should remove PTE_DEVMAP first and then add soft
dirty and uffd_wp.
Thanks,
Chunyan
>
> > endmenu # "Kernel features"
> >
> > menu "Boot options"
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index 5bcc73430829..c6d51fe9fc6f 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -26,6 +26,18 @@
> > #define _PAGE_DEVMAP 0
> > #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >
> > +#ifdef CONFIG_MEM_SOFT_DIRTY
> > +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> > +/*
> > + * BIT 4 is not involved into swap entry computation, so we
> > + * can borrow it for swap page soft-dirty tracking.
> > + */
> > +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> > +#else
> > +#define _PAGE_SOFT_DIRTY 0
> > +#define _PAGE_SWP_SOFT_DIRTY 0
> > +#endif /* CONFIG_MEM_SOFT_DIRTY */
> > +
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > /*
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 089f3c9f56a3..d41507919ef2 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >
> > static inline pte_t pte_mkdirty(pte_t pte)
> > {
> > - return __pte(pte_val(pte) | _PAGE_DIRTY);
> > + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> > }
> >
> > static inline pte_t pte_mkclean(pte_t pte)
> > @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> > return pte;
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pte_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> > +}
> > +
> > +static inline int pte_swp_soft_dirty(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> > +}
> > +
> > +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> > +}
> > +
> > +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> > +{
> > + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> > +}
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > #ifdef CONFIG_RISCV_ISA_SVNAPOT
> > #define pte_leaf_size(pte) (pte_napot(pte) ? \
> > napot_cont_size(napot_cont_order(pte)) :\
> > @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> > }
> >
> > +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> > +static inline int pmd_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> > +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_swp_soft_dirty(pmd_pte(pmd));
> > +}
> > +
> > +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> > +}
> > +
> > +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> > +{
> > + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> > +}
> > +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> > +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> > +
> > static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> > pmd_t *pmdp, pmd_t pmd)
> > {
> > @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> > * Format of swap PTE:
> > * bit 0: _PAGE_PRESENT (zero)
> > * bit 1 to 3: _PAGE_LEAF (zero)
> > + * bit 4: _PAGE_SWP_SOFT_DIRTY
> > * bit 5: _PAGE_PROT_NONE (zero)
> > * bit 6: exclusive marker
> > * bits 7 to 11: swap type
On 30/08/2024 04:31, Chunyan Zhang wrote:
> Hi Jinjie,
>
> On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>>
>>
>> On 2024/8/30 9:11, Chunyan Zhang wrote:
>>> The PTE bit(9) is reserved for software, now used by DEVMAP,
>>> this patch reuse bit(9) for soft-dirty which is enabled only
>>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
>>> and devmap will be mutually exclusive on RISC-V.
>>>
>>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
>>> available for swap PTEs on RISC-V systems.
>>>
>>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>>> ---
>>> arch/riscv/Kconfig | 27 ++++++++++-
>>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
>>> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
>>> 3 files changed, 106 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> index 0f3cd7c3a436..f1460fc01cd4 100644
>>> --- a/arch/riscv/Kconfig
>>> +++ b/arch/riscv/Kconfig
>>> @@ -39,7 +39,6 @@ config RISCV
>>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
>>> select ARCH_HAS_PMEM_API
>>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
>>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
>>> select ARCH_HAS_PTE_SPECIAL
>>> select ARCH_HAS_SET_DIRECT_MAP if MMU
>>> select ARCH_HAS_SET_MEMORY if MMU
>>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>>>
>>> If unsure, say N.
>>>
>>> +choice
>>> + prompt "PET RSW Bit(9) used for"
>>> + default RISCV_HAS_PTE_DEVMEP
>>> + depends on MMU && 64BIT
>>> + help
>>> + RISC-V PTE bit(9) is reserved for software, and used by more than
>>> + one kernel features which cannot be supported at the same time.
>>> + So we have to select one for it.
>>> +
>>> +config RISCV_HAS_PTE_DEVMEP
>>> + bool "DEVMAP mark"
>>> + select ARCH_HAS_PTE_DEVMAP
>>> + help
>>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
>>> + PTEs support to function.
>>> +
>>> + So if you want to use ZONE_DEVICE, select this.
>>> +
>>> +config RISCV_HAS_SOFT_DIRTY
>>> + bool "soft dirty"
>>> + select HAVE_ARCH_SOFT_DIRTY
>>> + help
>>> + The PTE bit(9) is used for soft-dirty tracking.
>>> +
>>> +endchoice
>>> +
>> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
>> riscv will too:
>>
>> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> Thanks for sharing, I didn't notice this.
> It looks like we should remove PTE_DEVMAP first and then add soft
> dirty and uffd_wp.
I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
should keep going with your patchset and we can still remove devmap later.
Thanks,
Alex
>
> Thanks,
> Chunyan
>
>>> endmenu # "Kernel features"
>>>
>>> menu "Boot options"
>>> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
>>> index 5bcc73430829..c6d51fe9fc6f 100644
>>> --- a/arch/riscv/include/asm/pgtable-bits.h
>>> +++ b/arch/riscv/include/asm/pgtable-bits.h
>>> @@ -26,6 +26,18 @@
>>> #define _PAGE_DEVMAP 0
>>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>>>
>>> +#ifdef CONFIG_MEM_SOFT_DIRTY
>>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
>>> +/*
>>> + * BIT 4 is not involved into swap entry computation, so we
>>> + * can borrow it for swap page soft-dirty tracking.
>>> + */
>>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
>>> +#else
>>> +#define _PAGE_SOFT_DIRTY 0
>>> +#define _PAGE_SWP_SOFT_DIRTY 0
>>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>> +
>>> #define _PAGE_TABLE _PAGE_PRESENT
>>>
>>> /*
>>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>>> index 089f3c9f56a3..d41507919ef2 100644
>>> --- a/arch/riscv/include/asm/pgtable.h
>>> +++ b/arch/riscv/include/asm/pgtable.h
>>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>>
>>> static inline pte_t pte_mkdirty(pte_t pte)
>>> {
>>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
>>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>>> }
>>>
>>> static inline pte_t pte_mkclean(pte_t pte)
>>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>>> return pte;
>>> }
>>>
>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>> +static inline int pte_soft_dirty(pte_t pte)
>>> +{
>>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
>>> +}
>>> +
>>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>>> +}
>>> +
>>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>>> +}
>>> +
>>> +static inline int pte_swp_soft_dirty(pte_t pte)
>>> +{
>>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
>>> +}
>>> +
>>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>>> +}
>>> +
>>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>>> +{
>>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>>> +}
>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>> +
>>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
>>> #define pte_leaf_size(pte) (pte_napot(pte) ? \
>>> napot_cont_size(napot_cont_order(pte)) :\
>>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
>>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
>>> }
>>>
>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>> +static inline int pmd_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_soft_dirty(pmd_pte(pmd));
>>> +}
>>> +
>>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_swp_soft_dirty(pmd_pte(pmd));
>>> +}
>>> +
>>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>>> +}
>>> +
>>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>>> +{
>>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>>> +}
>>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>> +
>>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
>>> pmd_t *pmdp, pmd_t pmd)
>>> {
>>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>>> * Format of swap PTE:
>>> * bit 0: _PAGE_PRESENT (zero)
>>> * bit 1 to 3: _PAGE_LEAF (zero)
>>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
>>> * bit 5: _PAGE_PROT_NONE (zero)
>>> * bit 6: exclusive marker
>>> * bits 7 to 11: swap type
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi Alex,
On Tue, 5 Nov 2024 at 21:14, Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> On 30/08/2024 04:31, Chunyan Zhang wrote:
> > Hi Jinjie,
> >
> > On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
> >>
> >>
> >> On 2024/8/30 9:11, Chunyan Zhang wrote:
> >>> The PTE bit(9) is reserved for software, now used by DEVMAP,
> >>> this patch reuse bit(9) for soft-dirty which is enabled only
> >>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
> >>> and devmap will be mutually exclusive on RISC-V.
> >>>
> >>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
> >>> available for swap PTEs on RISC-V systems.
> >>>
> >>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
> >>> ---
> >>> arch/riscv/Kconfig | 27 ++++++++++-
> >>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
> >>> arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++-
> >>> 3 files changed, 106 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >>> index 0f3cd7c3a436..f1460fc01cd4 100644
> >>> --- a/arch/riscv/Kconfig
> >>> +++ b/arch/riscv/Kconfig
> >>> @@ -39,7 +39,6 @@ config RISCV
> >>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> >>> select ARCH_HAS_PMEM_API
> >>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
> >>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
> >>> select ARCH_HAS_PTE_SPECIAL
> >>> select ARCH_HAS_SET_DIRECT_MAP if MMU
> >>> select ARCH_HAS_SET_MEMORY if MMU
> >>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
> >>>
> >>> If unsure, say N.
> >>>
> >>> +choice
> >>> + prompt "PET RSW Bit(9) used for"
> >>> + default RISCV_HAS_PTE_DEVMEP
> >>> + depends on MMU && 64BIT
> >>> + help
> >>> + RISC-V PTE bit(9) is reserved for software, and used by more than
> >>> + one kernel features which cannot be supported at the same time.
> >>> + So we have to select one for it.
> >>> +
> >>> +config RISCV_HAS_PTE_DEVMEP
> >>> + bool "DEVMAP mark"
> >>> + select ARCH_HAS_PTE_DEVMAP
> >>> + help
> >>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages need DEVMAP
> >>> + PTEs support to function.
> >>> +
> >>> + So if you want to use ZONE_DEVICE, select this.
> >>> +
> >>> +config RISCV_HAS_SOFT_DIRTY
> >>> + bool "soft dirty"
> >>> + select HAVE_ARCH_SOFT_DIRTY
> >>> + help
> >>> + The PTE bit(9) is used for soft-dirty tracking.
> >>> +
> >>> +endchoice
> >>> +
> >> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
> >> riscv will too:
> >>
> >> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
> > Thanks for sharing, I didn't notice this.
> > It looks like we should remove PTE_DEVMAP first and then add soft
> > dirty and uffd_wp.
>
>
> I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
> should keep going with your patchset and we can still remove devmap later.
Okay, then I will update the patchset with addressing your comments.
Thanks for the review,
Chunyan
>
> Thanks,
>
> Alex
>
>
> >
> > Thanks,
> > Chunyan
> >
> >>> endmenu # "Kernel features"
> >>>
> >>> menu "Boot options"
> >>> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> >>> index 5bcc73430829..c6d51fe9fc6f 100644
> >>> --- a/arch/riscv/include/asm/pgtable-bits.h
> >>> +++ b/arch/riscv/include/asm/pgtable-bits.h
> >>> @@ -26,6 +26,18 @@
> >>> #define _PAGE_DEVMAP 0
> >>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
> >>>
> >>> +#ifdef CONFIG_MEM_SOFT_DIRTY
> >>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */
> >>> +/*
> >>> + * BIT 4 is not involved into swap entry computation, so we
> >>> + * can borrow it for swap page soft-dirty tracking.
> >>> + */
> >>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
> >>> +#else
> >>> +#define _PAGE_SOFT_DIRTY 0
> >>> +#define _PAGE_SWP_SOFT_DIRTY 0
> >>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> >>> +
> >>> #define _PAGE_TABLE _PAGE_PRESENT
> >>>
> >>> /*
> >>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> >>> index 089f3c9f56a3..d41507919ef2 100644
> >>> --- a/arch/riscv/include/asm/pgtable.h
> >>> +++ b/arch/riscv/include/asm/pgtable.h
> >>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
> >>>
> >>> static inline pte_t pte_mkdirty(pte_t pte)
> >>> {
> >>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
> >>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
> >>> }
> >>>
> >>> static inline pte_t pte_mkclean(pte_t pte)
> >>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
> >>> return pte;
> >>> }
> >>>
> >>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >>> +static inline int pte_soft_dirty(pte_t pte)
> >>> +{
> >>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
> >>> +}
> >>> +
> >>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
> >>> +}
> >>> +
> >>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
> >>> +}
> >>> +
> >>> +static inline int pte_swp_soft_dirty(pte_t pte)
> >>> +{
> >>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
> >>> +}
> >>> +
> >>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> >>> +}
> >>> +
> >>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> >>> +{
> >>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
> >>> +}
> >>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >>> +
> >>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
> >>> #define pte_leaf_size(pte) (pte_napot(pte) ? \
> >>> napot_cont_size(napot_cont_order(pte)) :\
> >>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> >>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> >>> }
> >>>
> >>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> >>> +static inline int pmd_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_soft_dirty(pmd_pte(pmd));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
> >>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_swp_soft_dirty(pmd_pte(pmd));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +
> >>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
> >>> +{
> >>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
> >>> +}
> >>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
> >>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> >>> +
> >>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> >>> pmd_t *pmdp, pmd_t pmd)
> >>> {
> >>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> >>> * Format of swap PTE:
> >>> * bit 0: _PAGE_PRESENT (zero)
> >>> * bit 1 to 3: _PAGE_LEAF (zero)
> >>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
> >>> * bit 5: _PAGE_PROT_NONE (zero)
> >>> * bit 6: exclusive marker
> >>> * bits 7 to 11: swap type
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 2024/11/5 21:14, Alexandre Ghiti wrote:
> On 30/08/2024 04:31, Chunyan Zhang wrote:
>> Hi Jinjie,
>>
>> On Fri, 30 Aug 2024 at 09:31, Jinjie Ruan <ruanjinjie@huawei.com> wrote:
>>>
>>>
>>> On 2024/8/30 9:11, Chunyan Zhang wrote:
>>>> The PTE bit(9) is reserved for software, now used by DEVMAP,
>>>> this patch reuse bit(9) for soft-dirty which is enabled only
>>>> if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty
>>>> and devmap will be mutually exclusive on RISC-V.
>>>>
>>>> To add swap PTE soft-dirty tracking, we borrow bit (4) which is
>>>> available for swap PTEs on RISC-V systems.
>>>>
>>>> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
>>>> ---
>>>> arch/riscv/Kconfig | 27 ++++++++++-
>>>> arch/riscv/include/asm/pgtable-bits.h | 12 +++++
>>>> arch/riscv/include/asm/pgtable.h | 69
>>>> ++++++++++++++++++++++++++-
>>>> 3 files changed, 106 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>>> index 0f3cd7c3a436..f1460fc01cd4 100644
>>>> --- a/arch/riscv/Kconfig
>>>> +++ b/arch/riscv/Kconfig
>>>> @@ -39,7 +39,6 @@ config RISCV
>>>> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
>>>> select ARCH_HAS_PMEM_API
>>>> select ARCH_HAS_PREPARE_SYNC_CORE_CMD
>>>> - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
>>>> select ARCH_HAS_PTE_SPECIAL
>>>> select ARCH_HAS_SET_DIRECT_MAP if MMU
>>>> select ARCH_HAS_SET_MEMORY if MMU
>>>> @@ -948,6 +947,32 @@ config RANDOMIZE_BASE
>>>>
>>>> If unsure, say N.
>>>>
>>>> +choice
>>>> + prompt "PET RSW Bit(9) used for"
>>>> + default RISCV_HAS_PTE_DEVMEP
>>>> + depends on MMU && 64BIT
>>>> + help
>>>> + RISC-V PTE bit(9) is reserved for software, and used by more
>>>> than
>>>> + one kernel features which cannot be supported at the same time.
>>>> + So we have to select one for it.
>>>> +
>>>> +config RISCV_HAS_PTE_DEVMEP
>>>> + bool "DEVMAP mark"
>>>> + select ARCH_HAS_PTE_DEVMAP
>>>> + help
>>>> + The PTE bit(9) is used for DEVMAP mark. ZONE_DEVICE pages
>>>> need DEVMAP
>>>> + PTEs support to function.
>>>> +
>>>> + So if you want to use ZONE_DEVICE, select this.
>>>> +
>>>> +config RISCV_HAS_SOFT_DIRTY
>>>> + bool "soft dirty"
>>>> + select HAVE_ARCH_SOFT_DIRTY
>>>> + help
>>>> + The PTE bit(9) is used for soft-dirty tracking.
>>>> +
>>>> +endchoice
>>>> +
>>> Hi, ARCH_HAS_PTE_DEVMAP will be removed in following patch, I guess
>>> riscv will too:
>>>
>>> https://lore.kernel.org/all/47c26640cd85f3db2e0a2796047199bb984d1b3f.1719386613.git-series.apopple@nvidia.com/
>> Thanks for sharing, I didn't notice this.
>> It looks like we should remove PTE_DEVMAP first and then add soft
>> dirty and uffd_wp.
>
>
> I have not seen any progress in the removal of PTE_DEVMAP so I'd say we
> should keep going with your patchset and we can still remove devmap later.
Sure, it is time to keep going on.
I started by implementing a patch similar to multiplexing bit 9, but
considering the above remove PTE_DEVMAP patch, so just gave it up.
>
> Thanks,
>
> Alex
>
>
>>
>> Thanks,
>> Chunyan
>>
>>>> endmenu # "Kernel features"
>>>>
>>>> menu "Boot options"
>>>> diff --git a/arch/riscv/include/asm/pgtable-bits.h
>>>> b/arch/riscv/include/asm/pgtable-bits.h
>>>> index 5bcc73430829..c6d51fe9fc6f 100644
>>>> --- a/arch/riscv/include/asm/pgtable-bits.h
>>>> +++ b/arch/riscv/include/asm/pgtable-bits.h
>>>> @@ -26,6 +26,18 @@
>>>> #define _PAGE_DEVMAP 0
>>>> #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */
>>>>
>>>> +#ifdef CONFIG_MEM_SOFT_DIRTY
>>>> +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software
>>>> dirty tracking */
>>>> +/*
>>>> + * BIT 4 is not involved into swap entry computation, so we
>>>> + * can borrow it for swap page soft-dirty tracking.
>>>> + */
>>>> +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER
>>>> +#else
>>>> +#define _PAGE_SOFT_DIRTY 0
>>>> +#define _PAGE_SWP_SOFT_DIRTY 0
>>>> +#endif /* CONFIG_MEM_SOFT_DIRTY */
>>>> +
>>>> #define _PAGE_TABLE _PAGE_PRESENT
>>>>
>>>> /*
>>>> diff --git a/arch/riscv/include/asm/pgtable.h
>>>> b/arch/riscv/include/asm/pgtable.h
>>>> index 089f3c9f56a3..d41507919ef2 100644
>>>> --- a/arch/riscv/include/asm/pgtable.h
>>>> +++ b/arch/riscv/include/asm/pgtable.h
>>>> @@ -428,7 +428,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte)
>>>>
>>>> static inline pte_t pte_mkdirty(pte_t pte)
>>>> {
>>>> - return __pte(pte_val(pte) | _PAGE_DIRTY);
>>>> + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
>>>> }
>>>>
>>>> static inline pte_t pte_mkclean(pte_t pte)
>>>> @@ -461,6 +461,38 @@ static inline pte_t pte_mkhuge(pte_t pte)
>>>> return pte;
>>>> }
>>>>
>>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>>> +static inline int pte_soft_dirty(pte_t pte)
>>>> +{
>>>> + return pte_val(pte) & _PAGE_SOFT_DIRTY;
>>>> +}
>>>> +
>>>> +static inline pte_t pte_mksoft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
>>>> +}
>>>> +
>>>> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY));
>>>> +}
>>>> +
>>>> +static inline int pte_swp_soft_dirty(pte_t pte)
>>>> +{
>>>> + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY;
>>>> +}
>>>> +
>>>> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
>>>> +}
>>>> +
>>>> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
>>>> +{
>>>> + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY));
>>>> +}
>>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>>> +
>>>> #ifdef CONFIG_RISCV_ISA_SVNAPOT
>>>> #define pte_leaf_size(pte) (pte_napot(pte)
>>>> ? \
>>>>
>>>> napot_cont_size(napot_cont_order(pte)) :\
>>>> @@ -751,6 +783,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd)
>>>> return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
>>>> }
>>>>
>>>> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
>>>> +static inline int pmd_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_soft_dirty(pmd_pte(pmd));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
>>>> +static inline int pmd_swp_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_swp_soft_dirty(pmd_pte(pmd));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +
>>>> +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
>>>> +{
>>>> + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)));
>>>> +}
>>>> +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
>>>> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
>>>> +
>>>> static inline void set_pmd_at(struct mm_struct *mm, unsigned long
>>>> addr,
>>>> pmd_t *pmdp, pmd_t pmd)
>>>> {
>>>> @@ -841,6 +907,7 @@ extern pmd_t pmdp_collapse_flush(struct
>>>> vm_area_struct *vma,
>>>> * Format of swap PTE:
>>>> * bit 0: _PAGE_PRESENT (zero)
>>>> * bit 1 to 3: _PAGE_LEAF (zero)
>>>> + * bit 4: _PAGE_SWP_SOFT_DIRTY
>>>> * bit 5: _PAGE_PROT_NONE (zero)
>>>> * bit 6: exclusive marker
>>>> * bits 7 to 11: swap type
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
© 2016 - 2026 Red Hat, Inc.