On Thu, Aug 29, 2024 at 01:48:40PM GMT, Jessica Zhang wrote:
> For concurrent writeback, the real time encoder is responsible for
> trigger flush and trigger start. Return early for trigger start and
> trigger flush for the concurrent writeback encoders.
>
> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 9d495a186eb8..47b5a5994234 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1493,6 +1493,7 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
> struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
> {
> struct dpu_hw_ctl *ctl;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
Please move one line up.
> int pending_kickoff_cnt;
> u32 ret = UINT_MAX;
>
> @@ -1509,6 +1510,15 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
>
> pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
>
> + /* Return early if encoder is writeback and in clone mode */
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
> + dpu_enc->cwb_mask) {
Alignment
> + DPU_DEBUG("encoder %d skip flush for concurrent writeback encoder\n",
> + DRMID(drm_enc));
> + return;
> + }
> +
> +
> if (extra_flush_bits && ctl->ops.update_pending_flush)
> ctl->ops.update_pending_flush(ctl, extra_flush_bits);
>
> @@ -1531,6 +1541,8 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
> */
> static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
> {
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys->parent);
> +
> if (!phys) {
> DPU_ERROR("invalid argument(s)\n");
> return;
> @@ -1541,6 +1553,13 @@ static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
> return;
> }
>
> + if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
> + dpu_enc->cwb_mask) {
Align to open bracket. Please adapt your editor (e.g. 'set cino=(0' in Vim).
> + DPU_DEBUG("encoder %d CWB enabled, skipping\n",
> + DRMID(phys->parent));
Single line, please.
> + return;
> + }
> +
> if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
> phys->ops.trigger_start(phys);
> }
>
> --
> 2.34.1
>
--
With best wishes
Dmitry