Document the bindings for STM32 COMBOPHY interface, used to support
the PCIe and USB3 stm32mp25 drivers.
Following entries can be used to tune caracterisation parameters
- st,output-micro-ohms and st,output-vswing-microvolt bindings entries
to tune the impedance and voltage swing using discrete simulation results
- st,rx-equalizer register to set the internal rx equalizer filter value.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
---
.../bindings/phy/st,stm32-combophy.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
diff --git a/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
new file mode 100644
index 000000000000..c33a843b83a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/st,stm32-combophy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY
+
+maintainers:
+ - Christian Bruel <christian.bruel@foss.st.com>
+
+description:
+ Single lane PHY shared (exclusive) between the USB3 and PCIe controllers.
+ Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1.
+
+properties:
+ compatible:
+ const: st,stm32mp25-combophy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+ description: |
+ The cells contain the following arguments.
+
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+
+ clocks:
+ minItems: 2
+ items:
+ - description: apb Bus clock mandatory to access registers.
+ - description: ker Internal RCC reference clock for USB3 or PCIe
+ - description: pad Optional on board clock input for PCIe only. Typically an
+ external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference
+ clock input instead of the ker
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: apb
+ - const: ker
+ - const: pad
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: phy
+
+ power-domains:
+ maxItems: 1
+
+ wakeup-source: true
+
+ interrupts:
+ maxItems: 1
+ description: interrupt used for wakeup
+
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
+ st,syscfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the SYSCON entry required for configuring PCIe
+ or USB3.
+
+ st,ssc-on:
+ type: boolean
+ description:
+ A boolean property whose presence indicates that the SSC for common clock
+ needs to be set.
+
+ st,rx-equalizer:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ default: 2
+ description:
+ A 3 bit value to tune the RX fixed equalizer setting for optimal eye compliance
+
+ st,output-micro-ohms:
+ minimum: 3999000
+ maximum: 6090000
+ default: 4968000
+ description:
+ A value property to tune the Single Ended Output Impedance, simulations results
+ at 25C for a VDDP=0.8V. The hardware accepts discrete values in this range.
+
+ st,output-vswing-microvolt:
+ minimum: 442000
+ maximum: 803000
+ default: 803000
+ description:
+ A value property in microvolt to tune the Single Ended Output Voltage Swing to change the
+ Vlo, Vhi for a VDDP = 0.8V. The hardware accepts discrete values in this range.
+
+required:
+ - compatible
+ - reg
+ - st,syscfg
+ - '#phy-cells'
+ - resets
+ - reset-names
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ required:
+ - wakeup-source
+ then:
+ anyOf:
+ - required: [interrupts]
+ - required: [interrupts-extended]
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+
+ combophy: phy@480c0000 {
+ compatible = "st,stm32mp25-combophy";
+ reg = <0x480c0000 0x1000>;
+ #phy-cells = <1>;
+ clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
+ clock-names = "apb", "ker";
+ resets = <&rcc USB3PCIEPHY_R>;
+ reset-names = "phy";
+ st,syscfg = <&syscfg>;
+ access-controllers = <&rifsc 67>;
+ power-domains = <&CLUSTER_PD>;
+ wakeup-source;
+ interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+ };
+...
--
2.34.1On 27/08/2024 14:24, Christian Bruel wrote: > Document the bindings for STM32 COMBOPHY interface, used to support > the PCIe and USB3 stm32mp25 drivers. > Following entries can be used to tune caracterisation parameters > - st,output-micro-ohms and st,output-vswing-microvolt bindings entries > to tune the impedance and voltage swing using discrete simulation results > - st,rx-equalizer register to set the internal rx equalizer filter value. > > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> v1? Or v3? > --- > .../bindings/phy/st,stm32-combophy.yaml | 144 ++++++++++++++++++ > 1 file changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml > new file mode 100644 > index 000000000000..c33a843b83a3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml Filename matching compatible. > @@ -0,0 +1,144 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/st,stm32-combophy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY > + > +maintainers: > + - Christian Bruel <christian.bruel@foss.st.com> > + > +description: > + Single lane PHY shared (exclusive) between the USB3 and PCIe controllers. > + Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1. > + > +properties: > + compatible: > + const: st,stm32mp25-combophy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 1 > + description: | > + The cells contain the following arguments. > + > + - description: The PHY type That's some sort of mess. Is it schema within description or schema? Why two descriptions? > + enum: > + - PHY_TYPE_USB3 > + - PHY_TYPE_PCIE > + ... > +required: > + - compatible > + - reg > + - st,syscfg > + - '#phy-cells' > + - resets > + - reset-names > + - clocks > + - clock-names > + > +allOf: > + - if: > + required: > + - wakeup-source > + then: > + anyOf: > + - required: [interrupts] > + - required: [interrupts-extended] > + I do not see any improvements. The tag you received was CONDITIONAL. If you do not apply the comments, you cannot just apply the tag. Best regards, Krzysztof
On 8/27/24 15:23, Krzysztof Kozlowski wrote: > On 27/08/2024 14:24, Christian Bruel wrote: >> Document the bindings for STM32 COMBOPHY interface, used to support >> the PCIe and USB3 stm32mp25 drivers. >> Following entries can be used to tune caracterisation parameters >> - st,output-micro-ohms and st,output-vswing-microvolt bindings entries >> to tune the impedance and voltage swing using discrete simulation results >> - st,rx-equalizer register to set the internal rx equalizer filter value. >> >> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> >> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> > v1? Or v3? sorry, forgot to update Subject: it is v3, will resend a v4 with your further comments Regards Christian > >> --- >> .../bindings/phy/st,stm32-combophy.yaml | 144 ++++++++++++++++++ >> 1 file changed, 144 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml >> new file mode 100644 >> index 000000000000..c33a843b83a3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/st,stm32-combophy.yaml > Filename matching compatible. ok > >> @@ -0,0 +1,144 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/st,stm32-combophy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY >> + >> +maintainers: >> + - Christian Bruel <christian.bruel@foss.st.com> >> + >> +description: >> + Single lane PHY shared (exclusive) between the USB3 and PCIe controllers. >> + Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1. >> + >> +properties: >> + compatible: >> + const: st,stm32mp25-combophy >> + >> + reg: >> + maxItems: 1 >> + >> + "#phy-cells": >> + const: 1 >> + description: | >> + The cells contain the following arguments. >> + >> + - description: The PHY type > That's some sort of mess. Is it schema within description or schema? Why > two descriptions? yes, indeed >> + enum: >> + - PHY_TYPE_USB3 >> + - PHY_TYPE_PCIE >> + > ... > >> +required: >> + - compatible >> + - reg >> + - st,syscfg >> + - '#phy-cells' >> + - resets >> + - reset-names >> + - clocks >> + - clock-names >> + >> +allOf: >> + - if: >> + required: >> + - wakeup-source >> + then: >> + anyOf: >> + - required: [interrupts] >> + - required: [interrupts-extended] >> + > I do not see any improvements. > > The tag you received was CONDITIONAL. If you do not apply the comments, > you cannot just apply the tag. my mistake again. > Best regards, > Krzysztof >
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