Describe PCIe3 controller and PHY. Also add required system resources like
regulators, clocks, interrupts and registers configuration for PCIe3.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 ++++++++++++++++++++++++-
1 file changed, 204 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 74b694e74705..55b81e7de1c7 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -744,7 +744,7 @@ gcc: clock-controller@100000 {
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
- <0>,
+ <&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
@@ -2879,6 +2879,209 @@ mmss_noc: interconnect@1780000 {
#interconnect-cells = <2>;
};
+ pcie3: pci@1bd0000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01bd0000 0 0x3000>,
+ <0 0x78000000 0 0xf1d>,
+ <0 0x78000f40 0 0xa8>,
+ <0 0x78001000 0 0x1000>,
+ <0 0x78100000 0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x78200000 0 0x100000>,
+ <0x02000000 0 0x78300000 0 0x78300000 0 0x3d00000>;
+ bus-range = <0 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <3>;
+ num-lanes = <8>;
+
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 237 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3_PIPE_CLK_SRC>,
+ <&gcc GCC_PCIE_3_AUX_CLK>,
+ <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+ clock-names = "pipe_clk_src",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_south_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3_BCR>,
+ <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_3_GDSC>;
+
+ phys = <&pcie3_phy>;
+ phy-names = "pciephy";
+
+ operating-points-v2 = <&pcie3_opp_table>;
+
+ status = "disabled";
+
+ pcie3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 1 x4 and GEN 2 x2*/
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 1 x8 and GEN 2 X4 */
+ opp-20000000 {
+ opp-hz = /bits/ 64 <20000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <2000000 1>;
+ };
+
+ /* GEN 2 x8 */
+ opp-40000000 {
+ opp-hz = /bits/ 64 <40000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <4000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 3 x4 and GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3938000 1>;
+ };
+
+ /* GEN 3 x8 and GEN 4 x4 */
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <7876000 1>;
+ };
+
+ /* GEN 4 x8 */
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <15753000 1>;
+ };
+ };
+ };
+
+ pcie3_phy: phy@1be0000 {
+ compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
+ reg = <0 0x01be0000 0 0x10000>;
+
+ clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
+ <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_3_PIPE_CLK>,
+ <&gcc GCC_PCIE_3_PIPEDIV2_CLK>,
+ <&tcsr TCSR_PCIE_8L_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "phy_aux",
+ "pipe",
+ "pipediv2",
+ "clkref_en";
+
+ resets = <&gcc GCC_PCIE_3_PHY_BCR>,
+ <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie3_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
pcie6a: pci@1bf8000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
--
2.34.1On Mon, Aug 26, 2024 at 11:36:27PM -0700, Qiang Yu wrote: > Describe PCIe3 controller and PHY. Also add required system resources like > regulators, clocks, interrupts and registers configuration for PCIe3. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 ++++++++++++++++++++++++- Why DTS is mixed with the drivers? This patchset is organized in confusing way. Please use standard upstream submission process - DTS is always the last in the patchset (or separate). Best regards, Krzysztof
On 27.08.2024 8:36 AM, Qiang Yu wrote:
> Describe PCIe3 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe3.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 ++++++++++++++++++++++++-
> 1 file changed, 204 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 74b694e74705..55b81e7de1c7 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -744,7 +744,7 @@ gcc: clock-controller@100000 {
>
> clocks = <&bi_tcxo_div2>,
> <&sleep_clk>,
> - <0>,
> + <&pcie3_phy>,
> <&pcie4_phy>,
> <&pcie5_phy>,
> <&pcie6a_phy>,
> @@ -2879,6 +2879,209 @@ mmss_noc: interconnect@1780000 {
> #interconnect-cells = <2>;
> };
>
> + pcie3: pci@1bd0000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-x1e80100";
> + reg = <0 0x01bd0000 0 0x3000>,
> + <0 0x78000000 0 0xf1d>,
> + <0 0x78000f40 0 0xa8>,
> + <0 0x78001000 0 0x1000>,
> + <0 0x78100000 0 0x100000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config";
There's a "mhi" region at 0x01bd3000, 0x1000-wide too, please add it
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0 0x00000000 0 0x78200000 0 0x100000>,
> + <0x02000000 0 0x78300000 0 0x78300000 0 0x3d00000>;
There's 64bit BAR space as well:
<0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
> + bus-range = <0 0xff>;
0x00 please
> +
> + dma-coherent;
> +
> + linux,pci-domain = <3>;
> + num-lanes = <8>;
> +
> + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0",
> + "msi1",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 0 220 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 0 221 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 0 237 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 0 238 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_3_PIPE_CLK_SRC>,
We don't toggle source clocks from dt, this is upstream of the pipe
div clocks and is taken care of by the common clock framework,
please drop.
> + <&gcc GCC_PCIE_3_AUX_CLK>,
> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK
> + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
> + clock-names = "pipe_clk_src",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "noc_aggr",
> + "cnoc_sf_axi";
> +
> + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&pcie_south_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "pcie-mem",
> + "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_3_BCR>,
> + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
> + reset-names = "pci",
> + "link_down";
> +
> + power-domains = <&gcc GCC_PCIE_3_GDSC>;
> +
> + phys = <&pcie3_phy>;
> + phy-names = "pciephy";
> +
> + operating-points-v2 = <&pcie3_opp_table>;
> +
> + status = "disabled";
> +
> + pcie3_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /* GEN 1 x1 */
> + opp-2500000 {
> + opp-hz = /bits/ 64 <2500000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <250000 1>;
> + };
> +
> + /* GEN 1 x2 and GEN 2 x1 */
> + opp-5000000 {
> + opp-hz = /bits/ 64 <5000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <500000 1>;
> + };
> +
> + /* GEN 1 x4 and GEN 2 x2*/
Missing ' '
> + opp-10000000 {
> + opp-hz = /bits/ 64 <10000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + opp-peak-kBps = <1000000 1>;
> + };
> +
> + /* GEN 1 x8 and GEN 2 X4 */
Inconsistent capitalization, please use lowercase 'x'
[...]
> + pcie3_phy: phy@1be0000 {
> + compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
> + reg = <0 0x01be0000 0 0x10000>;
> +
> + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
This clock doesn't belong here, the PHY is clocked by PHY_AUX
> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
This is unnecessary as commented before
> + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_3_PIPE_CLK>,
> + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>,
> + <&tcsr TCSR_PCIE_8L_CLKREF_EN>;
This should be the 'ref' here
Konrad
On 8/27/2024 6:42 PM, Konrad Dybcio wrote:
> On 27.08.2024 8:36 AM, Qiang Yu wrote:
>> Describe PCIe3 controller and PHY. Also add required system resources like
>> regulators, clocks, interrupts and registers configuration for PCIe3.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 ++++++++++++++++++++++++-
>> 1 file changed, 204 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 74b694e74705..55b81e7de1c7 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -744,7 +744,7 @@ gcc: clock-controller@100000 {
>>
>> clocks = <&bi_tcxo_div2>,
>> <&sleep_clk>,
>> - <0>,
>> + <&pcie3_phy>,
>> <&pcie4_phy>,
>> <&pcie5_phy>,
>> <&pcie6a_phy>,
>> @@ -2879,6 +2879,209 @@ mmss_noc: interconnect@1780000 {
>> #interconnect-cells = <2>;
>> };
>>
>> + pcie3: pci@1bd0000 {
>> + device_type = "pci";
>> + compatible = "qcom,pcie-x1e80100";
>> + reg = <0 0x01bd0000 0 0x3000>,
>> + <0 0x78000000 0 0xf1d>,
>> + <0 0x78000f40 0 0xa8>,
>> + <0 0x78001000 0 0x1000>,
>> + <0 0x78100000 0 0x100000>;
>> + reg-names = "parf",
>> + "dbi",
>> + "elbi",
>> + "atu",
>> + "config";
> There's a "mhi" region at 0x01bd3000, 0x1000-wide too, please add it
>
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0 0x00000000 0 0x78200000 0 0x100000>,
>> + <0x02000000 0 0x78300000 0 0x78300000 0 0x3d00000>;
> There's 64bit BAR space as well:
>
> <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
>
>> + bus-range = <0 0xff>;
> 0x00 please
>
>> +
>> + dma-coherent;
>> +
>> + linux,pci-domain = <3>;
>> + num-lanes = <8>;
>> +
>> + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi0",
>> + "msi1",
>> + "msi2",
>> + "msi3",
>> + "msi4",
>> + "msi5",
>> + "msi6",
>> + "msi7";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 0 220 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 0 0 221 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 0 0 237 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 0 0 238 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_PCIE_3_PIPE_CLK_SRC>,
> We don't toggle source clocks from dt, this is upstream of the pipe
> div clocks and is taken care of by the common clock framework,
> please drop.
GCC_PCIE_3_PIPE_CLK_SRC is a clk mux. The enable and disable callback
provided in clk driver is used to switch between pipe_clk and XO,
respectively. If we drop GCC_PCIE_3_PIPE_CLK_SRC here, that means
the mux will be XO until pipediv2 clk is enabled. I need to do some
experiment to check this. Will update in thread.
Thanks,
Qiang
>> + <&gcc GCC_PCIE_3_AUX_CLK>,
>> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
>> + <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
> GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK
>
>> + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
>> + clock-names = "pipe_clk_src",
>> + "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a",
>> + "noc_aggr",
>> + "cnoc_sf_axi";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + interconnects = <&pcie_south_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "pcie-mem",
>> + "cpu-pcie";
>> +
>> + resets = <&gcc GCC_PCIE_3_BCR>,
>> + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
>> + reset-names = "pci",
>> + "link_down";
>> +
>> + power-domains = <&gcc GCC_PCIE_3_GDSC>;
>> +
>> + phys = <&pcie3_phy>;
>> + phy-names = "pciephy";
>> +
>> + operating-points-v2 = <&pcie3_opp_table>;
>> +
>> + status = "disabled";
>> +
>> + pcie3_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /* GEN 1 x1 */
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <250000 1>;
>> + };
>> +
>> + /* GEN 1 x2 and GEN 2 x1 */
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <500000 1>;
>> + };
>> +
>> + /* GEN 1 x4 and GEN 2 x2*/
> Missing ' '
>
>> + opp-10000000 {
>> + opp-hz = /bits/ 64 <10000000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + opp-peak-kBps = <1000000 1>;
>> + };
>> +
>> + /* GEN 1 x8 and GEN 2 X4 */
> Inconsistent capitalization, please use lowercase 'x'
>
> [...]
>
>> + pcie3_phy: phy@1be0000 {
>> + compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
>> + reg = <0 0x01be0000 0 0x10000>;
>> +
>> + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
> This clock doesn't belong here, the PHY is clocked by PHY_AUX
>
>> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
> This is unnecessary as commented before
>
>> + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
>> + <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
>> + <&gcc GCC_PCIE_3_PIPE_CLK>,
>> + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>,
>> + <&tcsr TCSR_PCIE_8L_CLKREF_EN>;
> This should be the 'ref' here
>
> Konrad
On 8/28/2024 9:36 PM, Qiang Yu wrote:
>
> On 8/27/2024 6:42 PM, Konrad Dybcio wrote:
>> On 27.08.2024 8:36 AM, Qiang Yu wrote:
>>> Describe PCIe3 controller and PHY. Also add required system
>>> resources like
>>> regulators, clocks, interrupts and registers configuration for PCIe3.
>>>
>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205
>>> ++++++++++++++++++++++++-
>>> 1 file changed, 204 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>> b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>> index 74b694e74705..55b81e7de1c7 100644
>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>>> @@ -744,7 +744,7 @@ gcc: clock-controller@100000 {
>>> clocks = <&bi_tcxo_div2>,
>>> <&sleep_clk>,
>>> - <0>,
>>> + <&pcie3_phy>,
>>> <&pcie4_phy>,
>>> <&pcie5_phy>,
>>> <&pcie6a_phy>,
>>> @@ -2879,6 +2879,209 @@ mmss_noc: interconnect@1780000 {
>>> #interconnect-cells = <2>;
>>> };
>>> + pcie3: pci@1bd0000 {
>>> + device_type = "pci";
>>> + compatible = "qcom,pcie-x1e80100";
>>> + reg = <0 0x01bd0000 0 0x3000>,
>>> + <0 0x78000000 0 0xf1d>,
>>> + <0 0x78000f40 0 0xa8>,
>>> + <0 0x78001000 0 0x1000>,
>>> + <0 0x78100000 0 0x100000>;
>>> + reg-names = "parf",
>>> + "dbi",
>>> + "elbi",
>>> + "atu",
>>> + "config";
>> There's a "mhi" region at 0x01bd3000, 0x1000-wide too, please add it
>>
>>> + #address-cells = <3>;
>>> + #size-cells = <2>;
>>> + ranges = <0x01000000 0 0x00000000 0 0x78200000 0
>>> 0x100000>,
>>> + <0x02000000 0 0x78300000 0 0x78300000 0 0x3d00000>;
>> There's 64bit BAR space as well:
>>
>> <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
>>
>>> + bus-range = <0 0xff>;
>> 0x00 please
>>
>>> +
>>> + dma-coherent;
>>> +
>>> + linux,pci-domain = <3>;
>>> + num-lanes = <8>;
>>> +
>>> + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "msi0",
>>> + "msi1",
>>> + "msi2",
>>> + "msi3",
>>> + "msi4",
>>> + "msi5",
>>> + "msi6",
>>> + "msi7";
>>> +
>>> + #interrupt-cells = <1>;
>>> + interrupt-map-mask = <0 0 0 0x7>;
>>> + interrupt-map = <0 0 0 1 &intc 0 0 0 220
>>> IRQ_TYPE_LEVEL_HIGH>,
>>> + <0 0 0 2 &intc 0 0 0 221 IRQ_TYPE_LEVEL_HIGH>,
>>> + <0 0 0 3 &intc 0 0 0 237 IRQ_TYPE_LEVEL_HIGH>,
>>> + <0 0 0 4 &intc 0 0 0 238 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> + clocks = <&gcc GCC_PCIE_3_PIPE_CLK_SRC>,
>> We don't toggle source clocks from dt, this is upstream of the pipe
>> div clocks and is taken care of by the common clock framework,
>> please drop.
> GCC_PCIE_3_PIPE_CLK_SRC is a clk mux. The enable and disable callback
> provided in clk driver is used to switch between pipe_clk and XO,
> respectively. If we drop GCC_PCIE_3_PIPE_CLK_SRC here, that means
> the mux will be XO until pipediv2 clk is enabled. I need to do some
> experiment to check this. Will update in thread.
>
> Thanks,
> Qiang
After removing GCC_PCIE_3_PIPE_CLK_SRC, I tested it and link was up.
Thanks,
Qiang
>>> + <&gcc GCC_PCIE_3_AUX_CLK>,
>>> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
>>> + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
>>> + <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
>>> + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
>>> + <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
>> GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK
>>
>>> + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
>>> + clock-names = "pipe_clk_src",
>>> + "aux",
>>> + "cfg",
>>> + "bus_master",
>>> + "bus_slave",
>>> + "slave_q2a",
>>> + "noc_aggr",
>>> + "cnoc_sf_axi";
>>> +
>>> + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
>>> + assigned-clock-rates = <19200000>;
>>> +
>>> + interconnects = <&pcie_south_anoc MASTER_PCIE_3
>>> QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>> + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
>>> + interconnect-names = "pcie-mem",
>>> + "cpu-pcie";
>>> +
>>> + resets = <&gcc GCC_PCIE_3_BCR>,
>>> + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
>>> + reset-names = "pci",
>>> + "link_down";
>>> +
>>> + power-domains = <&gcc GCC_PCIE_3_GDSC>;
>>> +
>>> + phys = <&pcie3_phy>;
>>> + phy-names = "pciephy";
>>> +
>>> + operating-points-v2 = <&pcie3_opp_table>;
>>> +
>>> + status = "disabled";
>>> +
>>> + pcie3_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + /* GEN 1 x1 */
>>> + opp-2500000 {
>>> + opp-hz = /bits/ 64 <2500000>;
>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>> + opp-peak-kBps = <250000 1>;
>>> + };
>>> +
>>> + /* GEN 1 x2 and GEN 2 x1 */
>>> + opp-5000000 {
>>> + opp-hz = /bits/ 64 <5000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>> + opp-peak-kBps = <500000 1>;
>>> + };
>>> +
>>> + /* GEN 1 x4 and GEN 2 x2*/
>> Missing ' '
>>
>>> + opp-10000000 {
>>> + opp-hz = /bits/ 64 <10000000>;
>>> + required-opps = <&rpmhpd_opp_low_svs>;
>>> + opp-peak-kBps = <1000000 1>;
>>> + };
>>> +
>>> + /* GEN 1 x8 and GEN 2 X4 */
>> Inconsistent capitalization, please use lowercase 'x'
>>
>> [...]
>>
>>> + pcie3_phy: phy@1be0000 {
>>> + compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
>>> + reg = <0 0x01be0000 0 0x10000>;
>>> +
>>> + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
>> This clock doesn't belong here, the PHY is clocked by PHY_AUX
>>
>>> + <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
>>> + <&rpmhcc RPMH_CXO_CLK>,
>> This is unnecessary as commented before
>>
>>> + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
>>> + <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
>>> + <&gcc GCC_PCIE_3_PIPE_CLK>,
>>> + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>,
>>> + <&tcsr TCSR_PCIE_8L_CLKREF_EN>;
>> This should be the 'ref' here
>>
>> Konrad
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