From: Mario Limonciello <mario.limonciello@amd.com>

On AMD processors the TSC has been reported drifting on and off for
various platforms.  This has been root caused to becaused by out of order
TSC and HPET counter values.  When the SoC supports RDTSCP or LFENCE_RDTSC
use ordered tsc reads instead.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/tsc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 94408a784c8e7..1c0cda1702bec 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -24,6 +24,9 @@ static inline cycles_t get_cycles(void)
 	if (!IS_ENABLED(CONFIG_X86_TSC) &&
 	    !cpu_feature_enabled(X86_FEATURE_TSC))
 		return 0;
+	if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC) ||
+	    cpu_feature_enabled(X86_FEATURE_RDTSCP))
+		return rdtsc_ordered();
 	return rdtsc();
 }
 #define get_cycles get_cycles
-- 
2.43.0

On Thu, Aug 22 2024 at 23:25, Mario Limonciello wrote:

Why is this hidden in a reply to the middle of a PCI patch series?

Sigh.

> From: Mario Limonciello <mario.limonciello@amd.com>
>
> On AMD processors the TSC has been reported drifting on and off for
> various platforms.  This has been root caused to becaused by out of order
> TSC and HPET counter values.  When the SoC supports RDTSCP or LFENCE_RDTSC
> use ordered tsc reads instead.

This really wants a fixes tag.

On 8/25/24 07:22, Thomas Gleixner wrote:
> On Thu, Aug 22 2024 at 23:25, Mario Limonciello wrote:
> 
> Why is this hidden in a reply to the middle of a PCI patch series?
> 
> Sigh.

As I mentioned in my reply I didn't mean for this to go out at this 
time.  Sorry for the noise!

It's still under testing that it REALLY helps things.
It was in my working directory and I totally missed it when I sent this 
PCI series.

> 
>> From: Mario Limonciello <mario.limonciello@amd.com>
>>
>> On AMD processors the TSC has been reported drifting on and off for
>> various platforms.  This has been root caused to becaused by out of order
>> TSC and HPET counter values.  When the SoC supports RDTSCP or LFENCE_RDTSC
>> use ordered tsc reads instead.
> 
> This really wants a fixes tag.

Yes; assuming it really helps I will send it properly with tags and to 
the right lists.

On 8/22/24 23:25, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@amd.com>
> 
> On AMD processors the TSC has been reported drifting on and off for
> various platforms.  This has been root caused to becaused by out of order
> TSC and HPET counter values.  When the SoC supports RDTSCP or LFENCE_RDTSC
> use ordered tsc reads instead.
> 
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   arch/x86/include/asm/tsc.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
> index 94408a784c8e7..1c0cda1702bec 100644
> --- a/arch/x86/include/asm/tsc.h
> +++ b/arch/x86/include/asm/tsc.h
> @@ -24,6 +24,9 @@ static inline cycles_t get_cycles(void)
>   	if (!IS_ENABLED(CONFIG_X86_TSC) &&
>   	    !cpu_feature_enabled(X86_FEATURE_TSC))
>   		return 0;
> +	if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC) ||
> +	    cpu_feature_enabled(X86_FEATURE_RDTSCP))
> +		return rdtsc_ordered();
>   	return rdtsc();
>   }
>   #define get_cycles get_cycles

Sorry; this unrelated patch I didn't intend to include in the series, it 
was in my working directory by accident.  Please disregard it for now, 
but review the rest of the series.

Thanks!