[v2] clk: renesas: rzv2h-cpg: Add divider clock support

[PATCH v2 0/2] clk: renesas: rzv2h-cpg: Add divider clock support

Prabhakar posted 2 patches 1 year, 5 months ago

Diff against v1 v3
Download series mbox

There is a newer version of this series

drivers/clk/renesas/r9a09g057-cpg.c |  84 ++++++++++++++
drivers/clk/renesas/rzv2h-cpg.c     | 165 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h     |  14 +++
3 files changed, 263 insertions(+)

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[PATCH v2 0/2] clk: renesas: rzv2h-cpg: Add divider clock support

Posted by Prabhakar 1 year, 5 months ago

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add divider clock support and add clock and
reset entries for below IP blocks for RZ/V2H(P) SoC,
- GTM
- WDT
- RIIC
- SDHI

v1->v2
- Updated DDIV_PACK macro to accommodate width and dropped DDIV_DIVCTL_WIDTH
- Updated DDIV_GET_* macros
- Now doing rmw as some of the DIVCTLx require it

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: rzv2h-cpg: Add support for dynamic switching divider
    clocks
  clk: renesas: r9a09g057-cpg: Add clock and reset entries for
    GTM/RIIC/SDHI/WDT

 drivers/clk/renesas/r9a09g057-cpg.c |  84 ++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c     | 165 ++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     |  14 +++
 3 files changed, 263 insertions(+)

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2.34.1