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[PATCH v9 0/6] RISC-V: Detect and report speed of unaligned vector accesses

Jesse Taube posted 6 patches 2 months, 2 weeks ago
There is a newer version of this series
Documentation/arch/riscv/hwprobe.rst       |  16 +++
arch/riscv/Kconfig                         |  57 +++++++-
arch/riscv/include/asm/cpufeature.h        |  10 +-
arch/riscv/include/asm/entry-common.h      |  11 --
arch/riscv/include/asm/hwprobe.h           |   2 +-
arch/riscv/include/asm/vector.h            |   2 +
arch/riscv/include/uapi/asm/hwprobe.h      |   5 +
arch/riscv/kernel/Makefile                 |   3 +-
arch/riscv/kernel/copy-unaligned.h         |   5 +
arch/riscv/kernel/fpu.S                    |   4 +-
arch/riscv/kernel/sys_hwprobe.c            |  41 ++++++
arch/riscv/kernel/traps_misaligned.c       | 131 +++++++++++++++--
arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++--
arch/riscv/kernel/vec-copy-unaligned.S     |  58 ++++++++
arch/riscv/kernel/vector.c                 |   2 +-
15 files changed, 465 insertions(+), 38 deletions(-)
create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
[PATCH v9 0/6] RISC-V: Detect and report speed of unaligned vector accesses
Posted by Jesse Taube 2 months, 2 weeks ago 
Adds support for detecting and reporting the speed of unaligned vector
accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
adds Zicclsm to cpufeature and fixes the check for scalar unaligned
emulated all CPUs. The vec_misaligned_speed key keeps the same format
as the scalar unaligned access speed key.

This set does not emulate unaligned vector accesses on CPUs that do not
support them. Only reports if userspace can run them and speed of
unaligned vector accesses if supported.

The Zicclsm is patches are no longer related to this set.

Changes in v6:
 Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")

Changes in V8:
 Dropped Zicclsm
 s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
  to match RISCV_HWPROBE_MISALIGNED_SCALAR_*
 Rebased onto palmer/fixes (32d5f7add080a936e28ab4142bfeea6b06999789)

Changes in V9:
 Missed a RISCV_HWPROBE_VECTOR_MISALIGNED...

Jesse Taube (6):
  RISC-V: Check scalar unaligned access on all CPUs
  RISC-V: Scalar unaligned access emulated on hotplug CPUs
  RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
  RISC-V: Detect unaligned vector accesses supported
  RISC-V: Report vector unaligned access speed hwprobe
  RISC-V: hwprobe: Document unaligned vector perf key

 Documentation/arch/riscv/hwprobe.rst       |  16 +++
 arch/riscv/Kconfig                         |  57 +++++++-
 arch/riscv/include/asm/cpufeature.h        |  10 +-
 arch/riscv/include/asm/entry-common.h      |  11 --
 arch/riscv/include/asm/hwprobe.h           |   2 +-
 arch/riscv/include/asm/vector.h            |   2 +
 arch/riscv/include/uapi/asm/hwprobe.h      |   5 +
 arch/riscv/kernel/Makefile                 |   3 +-
 arch/riscv/kernel/copy-unaligned.h         |   5 +
 arch/riscv/kernel/fpu.S                    |   4 +-
 arch/riscv/kernel/sys_hwprobe.c            |  41 ++++++
 arch/riscv/kernel/traps_misaligned.c       | 131 +++++++++++++++--
 arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++--
 arch/riscv/kernel/vec-copy-unaligned.S     |  58 ++++++++
 arch/riscv/kernel/vector.c                 |   2 +-
 15 files changed, 465 insertions(+), 38 deletions(-)
 create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S

base-commit: 32d5f7add080a936e28ab4142bfeea6b06999789

-- 
2.45.2
Re: [PATCH v9 0/6] RISC-V: Detect and report speed of unaligned vector accesses
Posted by Palmer Dabbelt 1 month, 2 weeks ago 
On Tue, 20 Aug 2024 08:24:18 PDT (-0700), jesse@rivosinc.com wrote:
> Adds support for detecting and reporting the speed of unaligned vector
> accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
> adds Zicclsm to cpufeature and fixes the check for scalar unaligned
> emulated all CPUs. The vec_misaligned_speed key keeps the same format
> as the scalar unaligned access speed key.
>
> This set does not emulate unaligned vector accesses on CPUs that do not
> support them. Only reports if userspace can run them and speed of
> unaligned vector accesses if supported.
>
> The Zicclsm is patches are no longer related to this set.
>
> Changes in v6:
>  Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")
>
> Changes in V8:
>  Dropped Zicclsm
>  s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
>   to match RISCV_HWPROBE_MISALIGNED_SCALAR_*
>  Rebased onto palmer/fixes (32d5f7add080a936e28ab4142bfeea6b06999789)
>
> Changes in V9:
>  Missed a RISCV_HWPROBE_VECTOR_MISALIGNED...
>
> Jesse Taube (6):
>   RISC-V: Check scalar unaligned access on all CPUs
>   RISC-V: Scalar unaligned access emulated on hotplug CPUs
>   RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
>   RISC-V: Detect unaligned vector accesses supported
>   RISC-V: Report vector unaligned access speed hwprobe
>   RISC-V: hwprobe: Document unaligned vector perf key
>
>  Documentation/arch/riscv/hwprobe.rst       |  16 +++
>  arch/riscv/Kconfig                         |  57 +++++++-
>  arch/riscv/include/asm/cpufeature.h        |  10 +-
>  arch/riscv/include/asm/entry-common.h      |  11 --
>  arch/riscv/include/asm/hwprobe.h           |   2 +-
>  arch/riscv/include/asm/vector.h            |   2 +
>  arch/riscv/include/uapi/asm/hwprobe.h      |   5 +
>  arch/riscv/kernel/Makefile                 |   3 +-
>  arch/riscv/kernel/copy-unaligned.h         |   5 +
>  arch/riscv/kernel/fpu.S                    |   4 +-
>  arch/riscv/kernel/sys_hwprobe.c            |  41 ++++++
>  arch/riscv/kernel/traps_misaligned.c       | 131 +++++++++++++++--
>  arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++--
>  arch/riscv/kernel/vec-copy-unaligned.S     |  58 ++++++++
>  arch/riscv/kernel/vector.c                 |   2 +-
>  15 files changed, 465 insertions(+), 38 deletions(-)
>  create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
>
> base-commit: 32d5f7add080a936e28ab4142bfeea6b06999789

I get a 

arch/riscv/kernel/traps_smisaligned.c: In function 'check_vector_unaligned_access_emulated':
arch/riscv/kernel/traps_misaligned.c:591:9: error: unknown register name 'v0' in 'asm'
  591 |         __asm__ __volatile__ (
      |         ^~~~~~~

on rv32/defconfig.  Looks like just a missing Kconfg guard as this 
depends on V support in the toolchain.
Re: [PATCH v9 0/6] RISC-V: Detect and report speed of unaligned vector accesses
Posted by Charlie Jenkins 1 month, 2 weeks ago 
On Fri, Sep 20, 2024 at 05:57:22AM -0700, Palmer Dabbelt wrote:
> On Tue, 20 Aug 2024 08:24:18 PDT (-0700), jesse@rivosinc.com wrote:
> > Adds support for detecting and reporting the speed of unaligned vector
> > accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
> > adds Zicclsm to cpufeature and fixes the check for scalar unaligned
> > emulated all CPUs. The vec_misaligned_speed key keeps the same format
> > as the scalar unaligned access speed key.
> > 
> > This set does not emulate unaligned vector accesses on CPUs that do not
> > support them. Only reports if userspace can run them and speed of
> > unaligned vector accesses if supported.
> > 
> > The Zicclsm is patches are no longer related to this set.
> > 
> > Changes in v6:
> >  Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")
> > 
> > Changes in V8:
> >  Dropped Zicclsm
> >  s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
> >   to match RISCV_HWPROBE_MISALIGNED_SCALAR_*
> >  Rebased onto palmer/fixes (32d5f7add080a936e28ab4142bfeea6b06999789)
> > 
> > Changes in V9:
> >  Missed a RISCV_HWPROBE_VECTOR_MISALIGNED...
> > 
> > Jesse Taube (6):
> >   RISC-V: Check scalar unaligned access on all CPUs
> >   RISC-V: Scalar unaligned access emulated on hotplug CPUs
> >   RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
> >   RISC-V: Detect unaligned vector accesses supported
> >   RISC-V: Report vector unaligned access speed hwprobe
> >   RISC-V: hwprobe: Document unaligned vector perf key
> > 
> >  Documentation/arch/riscv/hwprobe.rst       |  16 +++
> >  arch/riscv/Kconfig                         |  57 +++++++-
> >  arch/riscv/include/asm/cpufeature.h        |  10 +-
> >  arch/riscv/include/asm/entry-common.h      |  11 --
> >  arch/riscv/include/asm/hwprobe.h           |   2 +-
> >  arch/riscv/include/asm/vector.h            |   2 +
> >  arch/riscv/include/uapi/asm/hwprobe.h      |   5 +
> >  arch/riscv/kernel/Makefile                 |   3 +-
> >  arch/riscv/kernel/copy-unaligned.h         |   5 +
> >  arch/riscv/kernel/fpu.S                    |   4 +-
> >  arch/riscv/kernel/sys_hwprobe.c            |  41 ++++++
> >  arch/riscv/kernel/traps_misaligned.c       | 131 +++++++++++++++--
> >  arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++--
> >  arch/riscv/kernel/vec-copy-unaligned.S     |  58 ++++++++
> >  arch/riscv/kernel/vector.c                 |   2 +-
> >  15 files changed, 465 insertions(+), 38 deletions(-)
> >  create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
> > 
> > base-commit: 32d5f7add080a936e28ab4142bfeea6b06999789
> 
> I get a
> 
> arch/riscv/kernel/traps_smisaligned.c: In function 'check_vector_unaligned_access_emulated':
> arch/riscv/kernel/traps_misaligned.c:591:9: error: unknown register name 'v0' in 'asm'
>  591 |         __asm__ __volatile__ (
>      |         ^~~~~~~
> 
> on rv32/defconfig.  Looks like just a missing Kconfg guard as this depends
> on V support in the toolchain.

There was an interesting iteraction here!
RISCV_PROBE_VECTOR_UNALIGNED_ACCESS was selecting
RISCV_VECTOR_MISALIGNED but that bypasses the depends on check of
RISCV_ISA_V. I'll send an update for Jesse with the fix for that one
patch.

- Charlie
Re: [PATCH v9 0/6] RISC-V: Detect and report speed of unaligned vector accesses
Posted by Charlie Jenkins 1 month, 2 weeks ago 
On Fri, Sep 20, 2024 at 11:01:10PM +0200, Charlie Jenkins wrote:
> On Fri, Sep 20, 2024 at 05:57:22AM -0700, Palmer Dabbelt wrote:
> > On Tue, 20 Aug 2024 08:24:18 PDT (-0700), jesse@rivosinc.com wrote:
> > > Adds support for detecting and reporting the speed of unaligned vector
> > > accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
> > > adds Zicclsm to cpufeature and fixes the check for scalar unaligned
> > > emulated all CPUs. The vec_misaligned_speed key keeps the same format
> > > as the scalar unaligned access speed key.
> > > 
> > > This set does not emulate unaligned vector accesses on CPUs that do not
> > > support them. Only reports if userspace can run them and speed of
> > > unaligned vector accesses if supported.
> > > 
> > > The Zicclsm is patches are no longer related to this set.
> > > 
> > > Changes in v6:
> > >  Added ("RISC-V: Scalar unaligned access emulated on hotplug CPUs")
> > > 
> > > Changes in V8:
> > >  Dropped Zicclsm
> > >  s/RISCV_HWPROBE_VECTOR_MISALIGNED/RISCV_HWPROBE_MISALIGNED_VECTOR/g
> > >   to match RISCV_HWPROBE_MISALIGNED_SCALAR_*
> > >  Rebased onto palmer/fixes (32d5f7add080a936e28ab4142bfeea6b06999789)
> > > 
> > > Changes in V9:
> > >  Missed a RISCV_HWPROBE_VECTOR_MISALIGNED...
> > > 
> > > Jesse Taube (6):
> > >   RISC-V: Check scalar unaligned access on all CPUs
> > >   RISC-V: Scalar unaligned access emulated on hotplug CPUs
> > >   RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
> > >   RISC-V: Detect unaligned vector accesses supported
> > >   RISC-V: Report vector unaligned access speed hwprobe
> > >   RISC-V: hwprobe: Document unaligned vector perf key
> > > 
> > >  Documentation/arch/riscv/hwprobe.rst       |  16 +++
> > >  arch/riscv/Kconfig                         |  57 +++++++-
> > >  arch/riscv/include/asm/cpufeature.h        |  10 +-
> > >  arch/riscv/include/asm/entry-common.h      |  11 --
> > >  arch/riscv/include/asm/hwprobe.h           |   2 +-
> > >  arch/riscv/include/asm/vector.h            |   2 +
> > >  arch/riscv/include/uapi/asm/hwprobe.h      |   5 +
> > >  arch/riscv/kernel/Makefile                 |   3 +-
> > >  arch/riscv/kernel/copy-unaligned.h         |   5 +
> > >  arch/riscv/kernel/fpu.S                    |   4 +-
> > >  arch/riscv/kernel/sys_hwprobe.c            |  41 ++++++
> > >  arch/riscv/kernel/traps_misaligned.c       | 131 +++++++++++++++--
> > >  arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++++++++++++--
> > >  arch/riscv/kernel/vec-copy-unaligned.S     |  58 ++++++++
> > >  arch/riscv/kernel/vector.c                 |   2 +-
> > >  15 files changed, 465 insertions(+), 38 deletions(-)
> > >  create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
> > > 
> > > base-commit: 32d5f7add080a936e28ab4142bfeea6b06999789
> > 
> > I get a
> > 
> > arch/riscv/kernel/traps_smisaligned.c: In function 'check_vector_unaligned_access_emulated':
> > arch/riscv/kernel/traps_misaligned.c:591:9: error: unknown register name 'v0' in 'asm'
> >  591 |         __asm__ __volatile__ (
> >      |         ^~~~~~~
> > 
> > on rv32/defconfig.  Looks like just a missing Kconfg guard as this depends
> > on V support in the toolchain.
> 
> There was an interesting iteraction here!
> RISCV_PROBE_VECTOR_UNALIGNED_ACCESS was selecting
> RISCV_VECTOR_MISALIGNED but that bypasses the depends on check of
> RISCV_ISA_V. I'll send an update for Jesse with the fix for that one
> patch.

I take it back, I am not able to reproduce this.
RISCV_PROBE_VECTOR_UNALIGNED_ACCESS is hidden behind "Vector unaligned
Accesses Support" which depends on RISCV_ISA_V. This function that is
erroring has the code:

#ifdef CONFIG_RISCV_VECTOR_MISALIGNED
void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused)
...

Since it is hidden behind CONFIG_RISCV_VECTOR_MISALIGNED, I am unsure
how it is possible that this error is leaking through. The error you
posted is also kind of odd because the first file you have is
"arch/riscv/kernel/traps_smisaligned.c" but the actual file is
"arch/riscv/kernel/traps_misaligned.c".

> - Charlie
>

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