The CMN PLL controller provides clocks to networking hardware blocks
on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi,
and produces output clocks at fixed rates. These output rates are
predetermined, and are unrelated to the input clock rate. The output
clocks are supplied to the Ethernet hardware such as PPE (packet
process engine) and the externally connected switch or PHY device.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++
2 files changed, 85 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
new file mode 100644
index 000000000000..7ad04b58a698
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Luo Jie <quic_luoj@quicinc.com>
+
+description:
+ The CMN PLL clock controller expects a reference input clock.
+ This reference clock is from the on-board Wi-Fi. The CMN PLL
+ supplies a number of fixed rate output clocks to the Ethernet
+ devices including PPE (packet process engine) and the connected
+ switch or PHY device.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-cmn-pll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The reference clock. The supported clock rates include
+ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
+ - description: The AHB clock
+ - description: The SYS clock
+ description:
+ The reference clock is the source clock of CMN PLL, which is from the
+ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
+ clock registers.
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ahb
+ - const: sys
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+ clock-controller@9b000 {
+ compatible = "qcom,ipq9574-cmn-pll";
+ reg = <0x0009b000 0x800>;
+ clocks = <&cmn_pll_ref_clk>,
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+ clock-names = "ref", "ahb", "sys";
+ #clock-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
new file mode 100644
index 000000000000..64b228659389
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+
+/* The output clocks from CMN PLL of IPQ9574. */
+#define PPE_353MHZ_CLK 0
+#define ETH0_50MHZ_CLK 1
+#define ETH1_50MHZ_CLK 2
+#define ETH2_50MHZ_CLK 3
+#define ETH_25MHZ_CLK 4
+#endif
--
2.34.1On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: > The CMN PLL controller provides clocks to networking hardware blocks > on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, > and produces output clocks at fixed rates. These output rates are > predetermined, and are unrelated to the input clock rate. The output > clocks are supplied to the Ethernet hardware such as PPE (packet > process engine) and the externally connected switch or PHY device. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ > 2 files changed, 85 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: > The CMN PLL controller provides clocks to networking hardware blocks > on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, > and produces output clocks at fixed rates. These output rates are > predetermined, and are unrelated to the input clock rate. The output > clocks are supplied to the Ethernet hardware such as PPE (packet > process engine) and the externally connected switch or PHY device. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ > 2 files changed, 85 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > new file mode 100644 > index 000000000000..7ad04b58a698 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CMN PLL Clock Controller on IPQ SoC > + > +maintainers: > + - Bjorn Andersson <andersson@kernel.org> > + - Luo Jie <quic_luoj@quicinc.com> > + > +description: > + The CMN PLL clock controller expects a reference input clock. You did not explain what is CMN. Is this some sort of acronym? Best regards, Krzysztof
On 8/21/2024 4:33 PM, Krzysztof Kozlowski wrote: > On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: >> The CMN PLL controller provides clocks to networking hardware blocks >> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, >> and produces output clocks at fixed rates. These output rates are >> predetermined, and are unrelated to the input clock rate. The output >> clocks are supplied to the Ethernet hardware such as PPE (packet >> process engine) and the externally connected switch or PHY device. >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ >> include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ >> 2 files changed, 85 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >> new file mode 100644 >> index 000000000000..7ad04b58a698 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >> @@ -0,0 +1,70 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC >> + >> +maintainers: >> + - Bjorn Andersson <andersson@kernel.org> >> + - Luo Jie <quic_luoj@quicinc.com> >> + >> +description: >> + The CMN PLL clock controller expects a reference input clock. > > You did not explain what is CMN. Is this some sort of acronym? CMN is short form for 'common'. Since it is referred to as 'CMN' PLL in the hardware programming guides, we wanted the driver name to include it as well. The description can be updated as below to clarify the name and purpose of this hardware block. Hope this is fine. "The CMN PLL clock controller expects a reference input clock from the on-board Wi-Fi, and supplies a number of fixed rate output clocks to the Ethernet devices including PPE (packet process engine) and the connected switch or PHY device. The CMN (or 'common') PLL's only function is to enable clocks to Ethernet hardware used with the IPQ SoC and does not include any other function." > > Best regards, > Krzysztof > >
On 21/08/2024 18:08, Jie Luo wrote: > > > On 8/21/2024 4:33 PM, Krzysztof Kozlowski wrote: >> On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: >>> The CMN PLL controller provides clocks to networking hardware blocks >>> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, >>> and produces output clocks at fixed rates. These output rates are >>> predetermined, and are unrelated to the input clock rate. The output >>> clocks are supplied to the Ethernet hardware such as PPE (packet >>> process engine) and the externally connected switch or PHY device. >>> >>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >>> --- >>> .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ >>> include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ >>> 2 files changed, 85 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>> new file mode 100644 >>> index 000000000000..7ad04b58a698 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>> @@ -0,0 +1,70 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC >>> + >>> +maintainers: >>> + - Bjorn Andersson <andersson@kernel.org> >>> + - Luo Jie <quic_luoj@quicinc.com> >>> + >>> +description: >>> + The CMN PLL clock controller expects a reference input clock. >> >> You did not explain what is CMN. Is this some sort of acronym? > > CMN is short form for 'common'. Since it is referred to as 'CMN' > PLL in the hardware programming guides, we wanted the driver name > to include it as well. The description can be updated as below to > clarify the name and purpose of this hardware block. Hope this is > fine. > > "The CMN PLL clock controller expects a reference input clock > from the on-board Wi-Fi, and supplies a number of fixed rate > output clocks to the Ethernet devices including PPE (packet > process engine) and the connected switch or PHY device. The > CMN (or 'common') PLL's only function is to enable clocks to > Ethernet hardware used with the IPQ SoC and does not include > any other function." So the block is called "CMN" in hardware programming guide, without any explanation of the acronym? Best regards, Krzysztof
On 8/22/2024 2:29 PM, Krzysztof Kozlowski wrote: > On 21/08/2024 18:08, Jie Luo wrote: >> >> >> On 8/21/2024 4:33 PM, Krzysztof Kozlowski wrote: >>> On Tue, Aug 20, 2024 at 10:02:42PM +0800, Luo Jie wrote: >>>> The CMN PLL controller provides clocks to networking hardware blocks >>>> on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, >>>> and produces output clocks at fixed rates. These output rates are >>>> predetermined, and are unrelated to the input clock rate. The output >>>> clocks are supplied to the Ethernet hardware such as PPE (packet >>>> process engine) and the externally connected switch or PHY device. >>>> >>>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >>>> --- >>>> .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 70 ++++++++++++++++++++++ >>>> include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 15 +++++ >>>> 2 files changed, 85 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>>> new file mode 100644 >>>> index 000000000000..7ad04b58a698 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml >>>> @@ -0,0 +1,70 @@ >>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Qualcomm CMN PLL Clock Controller on IPQ SoC >>>> + >>>> +maintainers: >>>> + - Bjorn Andersson <andersson@kernel.org> >>>> + - Luo Jie <quic_luoj@quicinc.com> >>>> + >>>> +description: >>>> + The CMN PLL clock controller expects a reference input clock. >>> >>> You did not explain what is CMN. Is this some sort of acronym? >> >> CMN is short form for 'common'. Since it is referred to as 'CMN' >> PLL in the hardware programming guides, we wanted the driver name >> to include it as well. The description can be updated as below to >> clarify the name and purpose of this hardware block. Hope this is >> fine. >> >> "The CMN PLL clock controller expects a reference input clock >> from the on-board Wi-Fi, and supplies a number of fixed rate >> output clocks to the Ethernet devices including PPE (packet >> process engine) and the connected switch or PHY device. The >> CMN (or 'common') PLL's only function is to enable clocks to >> Ethernet hardware used with the IPQ SoC and does not include >> any other function." > > So the block is called "CMN" in hardware programming guide, without any > explanation of the acronym? Yes, I double checked again with our hardware team and the documentation. CMN is just a short form of "common" with no additional information in the guide. Thanks for review. > > Best regards, > Krzysztof >
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