iommu/amd: Update PASID, GATS, GLX, SNPAVICSUP feature related macros

[PATCH V2] iommu/amd: Update PASID, GATS, GLX, SNPAVICSUP feature related macros

Posted by Suravee Suthikulpanit 1 year, 5 months ago

Clean up and reorder them according to the bit index. There is no
functional change.

Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 drivers/iommu/amd/amd_iommu.h       |  5 -----
 drivers/iommu/amd/amd_iommu_types.h | 16 ++++++----------
 drivers/iommu/amd/init.c            |  8 +++-----
 3 files changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 2d5945c982bd..52e18b5f99fd 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -121,11 +121,6 @@ static inline bool check_feature2(u64 mask)
 	return (amd_iommu_efr2 & mask);
 }
 
-static inline int check_feature_gpt_level(void)
-{
-	return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
-}
-
 static inline bool amd_iommu_gt_ppr_supported(void)
 {
 	return (check_feature(FEATURE_GT) &&
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 2b76b5dedc1d..c9f9a598eb82 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -8,6 +8,7 @@
 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
 #define _ASM_X86_AMD_IOMMU_TYPES_H
 
+#include <linux/bitfield.h>
 #include <linux/iommu.h>
 #include <linux/types.h>
 #include <linux/mmu_notifier.h>
@@ -95,26 +96,21 @@
 #define FEATURE_GA		BIT_ULL(7)
 #define FEATURE_HE		BIT_ULL(8)
 #define FEATURE_PC		BIT_ULL(9)
-#define FEATURE_GATS_SHIFT	(12)
-#define FEATURE_GATS_MASK	(3ULL)
+#define FEATURE_GATS		GENMASK_ULL(13, 12)
+#define FEATURE_GLX		GENMASK_ULL(15, 14)
 #define FEATURE_GAM_VAPIC	BIT_ULL(21)
+#define FEATURE_PASMAX		GENMASK_ULL(36, 32)
 #define FEATURE_GIOSUP		BIT_ULL(48)
 #define FEATURE_HASUP		BIT_ULL(49)
 #define FEATURE_EPHSUP		BIT_ULL(50)
 #define FEATURE_HDSUP		BIT_ULL(52)
 #define FEATURE_SNP		BIT_ULL(63)
 
-#define FEATURE_PASID_SHIFT	32
-#define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
-
-#define FEATURE_GLXVAL_SHIFT	14
-#define FEATURE_GLXVAL_MASK	(0x03ULL << FEATURE_GLXVAL_SHIFT)
 
 /* Extended Feature 2 Bits */
-#define FEATURE_SNPAVICSUP_SHIFT	5
-#define FEATURE_SNPAVICSUP_MASK		(0x07ULL << FEATURE_SNPAVICSUP_SHIFT)
+#define FEATURE_SNPAVICSUP	GENMASK_ULL(7, 5)
 #define FEATURE_SNPAVICSUP_GAM(x) \
-	((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1)
+	(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
 
 /* Note:
  * The current driver only support 16-bit PASID.
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index c89d85b54a1a..6b15ce09e78d 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -2042,14 +2042,12 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
 		int glxval;
 		u64 pasmax;
 
-		pasmax = amd_iommu_efr & FEATURE_PASID_MASK;
-		pasmax >>= FEATURE_PASID_SHIFT;
+		pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr);
 		iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1;
 
 		BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK);
 
-		glxval   = amd_iommu_efr & FEATURE_GLXVAL_MASK;
-		glxval >>= FEATURE_GLXVAL_SHIFT;
+		glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr);
 
 		if (amd_iommu_max_glx_val == -1)
 			amd_iommu_max_glx_val = glxval;
@@ -3088,7 +3086,7 @@ static int __init early_amd_iommu_init(void)
 
 	/* 5 level guest page table */
 	if (cpu_feature_enabled(X86_FEATURE_LA57) &&
-	    check_feature_gpt_level() == GUEST_PGTABLE_5_LEVEL)
+	    FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL)
 		amd_iommu_gpt_level = PAGE_MODE_5_LEVEL;
 
 	/* Disable any previously enabled IOMMUs */
-- 
2.34.1

Re: [PATCH V2] iommu/amd: Update PASID, GATS, GLX, SNPAVICSUP feature related macros

Posted by Joerg Roedel 1 year, 5 months ago

On Fri, Aug 16, 2024 at 10:16:50PM +0000, Suravee Suthikulpanit wrote:
> Clean up and reorder them according to the bit index. There is no
> functional change.
> 
> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu.h       |  5 -----
>  drivers/iommu/amd/amd_iommu_types.h | 16 ++++++----------
>  drivers/iommu/amd/init.c            |  8 +++-----
>  3 files changed, 9 insertions(+), 20 deletions(-)

Applied, thanks.
>

Re: [PATCH V2] iommu/amd: Update PASID, GATS, GLX, SNPAVICSUP feature related macros

Posted by Jason Gunthorpe 1 year, 5 months ago

On Fri, Aug 16, 2024 at 10:16:50PM +0000, Suravee Suthikulpanit wrote:
> Clean up and reorder them according to the bit index. There is no
> functional change.
> 
> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
>  drivers/iommu/amd/amd_iommu.h       |  5 -----
>  drivers/iommu/amd/amd_iommu_types.h | 16 ++++++----------
>  drivers/iommu/amd/init.c            |  8 +++-----
>  3 files changed, 9 insertions(+), 20 deletions(-)

This is nicer! Thanks

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>

Jason

Re: [PATCH V2] iommu/amd: Update PASID, GATS, GLX, SNPAVICSUP feature related macros

Posted by Vasant Hegde 1 year, 5 months ago


On 8/17/2024 3:46 AM, Suravee Suthikulpanit wrote:
> Clean up and reorder them according to the bit index. There is no
> functional change.
> 
> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>

Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>

-Vasant

> ---
>  drivers/iommu/amd/amd_iommu.h       |  5 -----
>  drivers/iommu/amd/amd_iommu_types.h | 16 ++++++----------
>  drivers/iommu/amd/init.c            |  8 +++-----
>  3 files changed, 9 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
> index 2d5945c982bd..52e18b5f99fd 100644
> --- a/drivers/iommu/amd/amd_iommu.h
> +++ b/drivers/iommu/amd/amd_iommu.h
> @@ -121,11 +121,6 @@ static inline bool check_feature2(u64 mask)
>  	return (amd_iommu_efr2 & mask);
>  }
>  
> -static inline int check_feature_gpt_level(void)
> -{
> -	return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
> -}
> -
>  static inline bool amd_iommu_gt_ppr_supported(void)
>  {
>  	return (check_feature(FEATURE_GT) &&
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 2b76b5dedc1d..c9f9a598eb82 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -8,6 +8,7 @@
>  #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
>  #define _ASM_X86_AMD_IOMMU_TYPES_H
>  
> +#include <linux/bitfield.h>
>  #include <linux/iommu.h>
>  #include <linux/types.h>
>  #include <linux/mmu_notifier.h>
> @@ -95,26 +96,21 @@
>  #define FEATURE_GA		BIT_ULL(7)
>  #define FEATURE_HE		BIT_ULL(8)
>  #define FEATURE_PC		BIT_ULL(9)
> -#define FEATURE_GATS_SHIFT	(12)
> -#define FEATURE_GATS_MASK	(3ULL)
> +#define FEATURE_GATS		GENMASK_ULL(13, 12)
> +#define FEATURE_GLX		GENMASK_ULL(15, 14)
>  #define FEATURE_GAM_VAPIC	BIT_ULL(21)
> +#define FEATURE_PASMAX		GENMASK_ULL(36, 32)
>  #define FEATURE_GIOSUP		BIT_ULL(48)
>  #define FEATURE_HASUP		BIT_ULL(49)
>  #define FEATURE_EPHSUP		BIT_ULL(50)
>  #define FEATURE_HDSUP		BIT_ULL(52)
>  #define FEATURE_SNP		BIT_ULL(63)
>  
> -#define FEATURE_PASID_SHIFT	32
> -#define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
> -
> -#define FEATURE_GLXVAL_SHIFT	14
> -#define FEATURE_GLXVAL_MASK	(0x03ULL << FEATURE_GLXVAL_SHIFT)
>  
>  /* Extended Feature 2 Bits */
> -#define FEATURE_SNPAVICSUP_SHIFT	5
> -#define FEATURE_SNPAVICSUP_MASK		(0x07ULL << FEATURE_SNPAVICSUP_SHIFT)
> +#define FEATURE_SNPAVICSUP	GENMASK_ULL(7, 5)
>  #define FEATURE_SNPAVICSUP_GAM(x) \
> -	((x & FEATURE_SNPAVICSUP_MASK) >> FEATURE_SNPAVICSUP_SHIFT == 0x1)
> +	(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
>  
>  /* Note:
>   * The current driver only support 16-bit PASID.
> diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
> index c89d85b54a1a..6b15ce09e78d 100644
> --- a/drivers/iommu/amd/init.c
> +++ b/drivers/iommu/amd/init.c
> @@ -2042,14 +2042,12 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
>  		int glxval;
>  		u64 pasmax;
>  
> -		pasmax = amd_iommu_efr & FEATURE_PASID_MASK;
> -		pasmax >>= FEATURE_PASID_SHIFT;
> +		pasmax = FIELD_GET(FEATURE_PASMAX, amd_iommu_efr);
>  		iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1;
>  
>  		BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK);
>  
> -		glxval   = amd_iommu_efr & FEATURE_GLXVAL_MASK;
> -		glxval >>= FEATURE_GLXVAL_SHIFT;
> +		glxval = FIELD_GET(FEATURE_GLX, amd_iommu_efr);
>  
>  		if (amd_iommu_max_glx_val == -1)
>  			amd_iommu_max_glx_val = glxval;
> @@ -3088,7 +3086,7 @@ static int __init early_amd_iommu_init(void)
>  
>  	/* 5 level guest page table */
>  	if (cpu_feature_enabled(X86_FEATURE_LA57) &&
> -	    check_feature_gpt_level() == GUEST_PGTABLE_5_LEVEL)
> +	    FIELD_GET(FEATURE_GATS, amd_iommu_efr) == GUEST_PGTABLE_5_LEVEL)
>  		amd_iommu_gpt_level = PAGE_MODE_5_LEVEL;
>  
>  	/* Disable any previously enabled IOMMUs */