Introduce to the AST27XX INTC modules, which contain two conponents in
CPU die(12nm) and IO die(40mm) comunicating by SLI or LTPI protocol.

There are lots of device in IO die, which need to be serviced in
requested interrupt handler. As two die ICs, combine 32 interrupt source
in IO die into 1 interrupt in CPU die.

soc0_intc11 represent CPU die INTC, which each bit mapping to soc1_intcX.
soc1_intcX represent IO die INTC, which combines 32 interrupt sources.

Kevin Chen (2):
  dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC
  irqchip/aspeed-intc: Add support for 10 INTC interrupts on AST27XX
    platforms

 .../aspeed,ast2700-intc.yaml                  | 120 +++++++++++
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-aspeed-intc.c             | 198 ++++++++++++++++++
 3 files changed, 319 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
 create mode 100644 drivers/irqchip/irq-aspeed-intc.c

-- 
2.34.1

Support for the Aspeed Interrupt Controller found on Aspeed 7th Geration Silicon
SoCs.

ASPEED interrupt controller(INTC) maps the internal interrupt sources of
the AST27XX devices to an parent interrupt controller.

Changes since v2:
Combine the aspeed_intc_ic_of_init and aspeed_intc_ic_of_init_v2.
Switch raw_spin_lock_irqsave to scoped_guard and guard.
Fix the error of make dt_binding_check.
Refine the aspeed,ast2700-intc.yaml.


Kevin Chen (2):
  dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC
  irqchip/aspeed-intc: Add support for AST27XX INTC

 .../aspeed,ast2700-intc.yaml                  |  71 +++++++++
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-aspeed-intc.c             | 137 ++++++++++++++++++
 3 files changed, 209 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
 create mode 100644 drivers/irqchip/irq-aspeed-intc.c

-- 
2.34.1

On 14/08/2024 13:41, Kevin Chen wrote:
> Support for the Aspeed Interrupt Controller found on Aspeed 7th Geration Silicon
> SoCs.
> 
> ASPEED interrupt controller(INTC) maps the internal interrupt sources of
> the AST27XX devices to an parent interrupt controller.
> 
> Changes since v2:
> Combine the aspeed_intc_ic_of_init and aspeed_intc_ic_of_init_v2.
> Switch raw_spin_lock_irqsave to scoped_guard and guard.
> Fix the error of make dt_binding_check.
> Refine the aspeed,ast2700-intc.yaml.

It seems that entire Aspeed has troubles working with people in the
community. You do not address feedback, you ignore it and asks us to
re-review the same crap.

Before we proceed further:
1. Answer, inline, without confidentiality notice (after asking you this
5 times, I think you should fix it finally) that you:
 - agree (ack/ok/agree)
 - disagree with explanation why

2. Then double check that your new version implements everything above.

3. Then send new version (max once per 24h) with changelog and
versioning (just use `b4`).

If you keep ignoring step 1 and 2, you will annoy reviewers up to the
point of automatic NAK or being ignored.

Best regards,
Krzysztof