Add missing HS PHY IRQs to all 3 USB1 SS instances.

Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 326283822aee..254643650fa7 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3871,10 +3871,12 @@ usb_1_ss2: usb@a0f8800 {
 					       <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
 					  "dp_hs_phy_irq",
 					  "dm_hs_phy_irq",
 					  "ss_phy_irq";
@@ -4045,10 +4047,12 @@ usb_1_ss0: usb@a6f8800 {
 					       <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
 					  "dp_hs_phy_irq",
 					  "dm_hs_phy_irq",
 					  "ss_phy_irq";
@@ -4136,10 +4140,12 @@ usb_1_ss1: usb@a8f8800 {
 					       <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
 					  "dp_hs_phy_irq",
 					  "dm_hs_phy_irq",
 					  "ss_phy_irq";

---
base-commit: 61c01d2e181adfba02fe09764f9fca1de2be0dbe
change-id: 20240726-x1e80100-dts-usb-1-ss0-2-add-hs-phy-irqs-0d483addf0c5

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>

On 09/08/2024 12:12, Abel Vesa wrote:
> Add missing HS PHY IRQs to all 3 USB1 SS instances.
> 
> Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 326283822aee..254643650fa7 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3871,10 +3871,12 @@ usb_1_ss2: usb@a0f8800 {
>  					       <200000000>;
>  
>  			interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
>  					      <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
>  					      <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
>  					      <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
>  			interrupt-names = "pwr_event",
> +					  "hs_phy_irq",

I think current bindings disagree with this. If there is a binding
update, please post a link.

Best regards,
Krzysztof