Nuvoton MA35 SoCs support DWC2 USB controller.
Add the driver to drive the USB 2.0 PHY transceivers.

Signed-off-by: hpchen0 <hpchen0nvt@gmail.com>
---
 drivers/phy/Kconfig                 |   1 +
 drivers/phy/Makefile                |   1 +
 drivers/phy/nuvoton/Kconfig         |  13 +++
 drivers/phy/nuvoton/Makefile        |   3 +
 drivers/phy/nuvoton/phy-ma35-usb2.c | 160 ++++++++++++++++++++++++++++
 5 files changed, 178 insertions(+)
 create mode 100644 drivers/phy/nuvoton/Kconfig
 create mode 100644 drivers/phy/nuvoton/Makefile
 create mode 100644 drivers/phy/nuvoton/phy-ma35-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index dfab1c66b3e5..f73abff416be 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -95,6 +95,7 @@ source "drivers/phy/mediatek/Kconfig"
 source "drivers/phy/microchip/Kconfig"
 source "drivers/phy/motorola/Kconfig"
 source "drivers/phy/mscc/Kconfig"
+source "drivers/phy/nuvoton/Kconfig"
 source "drivers/phy/qualcomm/Kconfig"
 source "drivers/phy/ralink/Kconfig"
 source "drivers/phy/realtek/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 5fcbce5f9ab1..ebc399560da4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -25,6 +25,7 @@ obj-y					+= allwinner/	\
 					   microchip/	\
 					   motorola/	\
 					   mscc/	\
+					   nuvoton/	\
 					   qualcomm/	\
 					   ralink/	\
 					   realtek/	\
diff --git a/drivers/phy/nuvoton/Kconfig b/drivers/phy/nuvoton/Kconfig
new file mode 100644
index 000000000000..270ee2943287
--- /dev/null
+++ b/drivers/phy/nuvoton/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# PHY drivers for Nuvoton MA35 platforms
+#
+config PHY_MA35_USB
+	tristate "Nuvoton MA35 USB2.0 PHY driver"
+	depends on ARCH_MA35 || COMPILE_TEST
+	depends on OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB2.0 PHY on the Nuvoton MA35
+	  series SoCs.
+
diff --git a/drivers/phy/nuvoton/Makefile b/drivers/phy/nuvoton/Makefile
new file mode 100644
index 000000000000..85785e037d5f
--- /dev/null
+++ b/drivers/phy/nuvoton/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PHY_MA35_USB)		+= phy-ma35-usb2.o
diff --git a/drivers/phy/nuvoton/phy-ma35-usb2.c b/drivers/phy/nuvoton/phy-ma35-usb2.c
new file mode 100644
index 000000000000..061b31fcfbb1
--- /dev/null
+++ b/drivers/phy/nuvoton/phy-ma35-usb2.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Nuvoton Technology Corp.
+ */
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/* USB PHY Miscellaneous Control Register */
+#define MA35_SYS_REG_USBPMISCR	0x60
+#define PHY0POR			BIT(0)  /* PHY Power-On Reset Control Bit */
+#define PHY0SUSPEND			BIT(1)  /* PHY Suspend; 0: suspend, 1: operaion */
+#define PHY0COMN			BIT(2)  /* PHY Common Block Power-Down Control */
+#define PHY0DEVCKSTB			BIT(10) /* PHY 60 MHz UTMI clock stable bit */
+
+struct ma35_usb_phy {
+	struct clk *clk;
+	struct device *dev;
+	struct regmap *sysreg;
+};
+
+static int ma35_usb_phy_power_on(struct phy *phy)
+{
+	struct ma35_usb_phy *p_phy = phy_get_drvdata(phy);
+	unsigned long timeout;
+	unsigned int val;
+	int ret;
+
+	ret = clk_prepare_enable(p_phy->clk);
+	if (ret < 0) {
+		dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
+		return ret;
+	}
+
+	regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
+	if (val & PHY0SUSPEND) {
+		/*
+		 * USB PHY0 is in operation mode already
+		 * make sure USB PHY 60 MHz UTMI Interface Clock ready
+		 */
+		timeout = jiffies + msecs_to_jiffies(200);
+		while (time_before(jiffies, timeout)) {
+			regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
+			if (val & PHY0DEVCKSTB)
+				return 0;
+			usleep_range(1000, 1500);
+		}
+	}
+
+	/*
+	 * reset USB PHY0.
+	 * wait until USB PHY0 60 MHz UTMI Interface Clock ready
+	 */
+	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND));
+	timeout = jiffies + msecs_to_jiffies(200);
+	while (time_before(jiffies, timeout)) {
+		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
+		if (val & PHY0DEVCKSTB)
+			break;
+		usleep_range(1000, 1500);
+	}
+
+	/* make USB PHY0 enter operation mode */
+	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEND);
+
+	/* make sure USB PHY 60 MHz UTMI Interface Clock ready */
+	timeout = jiffies + msecs_to_jiffies(200);
+	while (time_before(jiffies, timeout)) {
+		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
+		if (val & PHY0DEVCKSTB)
+			return 0;
+		usleep_range(1000, 1500);
+	}
+
+	dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
+	ret = -ETIMEDOUT;
+
+	clk_disable_unprepare(p_phy->clk);
+	return ret;
+}
+
+static int ma35_usb_phy_power_off(struct phy *phy)
+{
+	struct ma35_usb_phy *p_phy = phy_get_drvdata(phy);
+
+	clk_disable_unprepare(p_phy->clk);
+	return 0;
+}
+
+static const struct phy_ops ma35_usb_phy_ops = {
+	.power_on = ma35_usb_phy_power_on,
+	.power_off = ma35_usb_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+static int ma35_usb_phy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *provider;
+	struct ma35_usb_phy *p_phy;
+	const char *clkgate;
+	struct phy *phy;
+
+	p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
+	if (!p_phy)
+		return -ENOMEM;
+
+	p_phy->dev = &pdev->dev;
+	platform_set_drvdata(pdev, p_phy);
+
+	p_phy->sysreg = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node, "nuvoton,sys");
+	if (IS_ERR(p_phy->sysreg))
+		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->sysreg),
+				     "Failed to get SYS registers\n");
+
+	/* enable clock */
+	of_property_read_string(p_phy->dev->of_node, "clock-enable", &clkgate);
+	p_phy->clk = devm_clk_get(p_phy->dev, clkgate);
+	if (IS_ERR(p_phy->clk))
+		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->clk),
+				     "Failed to get usb_phy clock\n");
+
+	phy = devm_phy_create(p_phy->dev, NULL, &ma35_usb_phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(&pdev->dev, PTR_ERR(phy), "Failed to create PHY\n");
+
+	phy_set_drvdata(phy, p_phy);
+
+	provider = devm_of_phy_provider_register(p_phy->dev, of_phy_simple_xlate);
+	if (IS_ERR(provider))
+		return dev_err_probe(&pdev->dev, PTR_ERR(provider),
+				     "Failed to register PHY provider\n");
+	return 0;
+}
+
+static const struct of_device_id ma35_usb_phy_of_match[] = {
+	{ .compatible = "nuvoton,ma35-usb2-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, ma35_usb_phy_of_match);
+
+static struct platform_driver ma35_usb_phy_driver = {
+	.probe		= ma35_usb_phy_probe,
+	.driver	= {
+		.name	= "ma35-usb2-phy",
+		.of_match_table = ma35_usb_phy_of_match,
+	},
+};
+module_platform_driver(ma35_usb_phy_driver);
+
+MODULE_DESCRIPTION("Nuvoton ma35 USB2.0 PHY driver");
+MODULE_AUTHOR("hpchen0nvt@gmail.com");
+MODULE_LICENSE("GPL");
-- 
2.25.1

On 29/07/2024 08:15, hpchen0 wrote:
> Nuvoton MA35 SoCs support DWC2 USB controller.
> Add the driver to drive the USB 2.0 PHY transceivers.
> 
> Signed-off-by: hpchen0 <hpchen0nvt@gmail.com>

> +
> +	ret = clk_prepare_enable(p_phy->clk);
> +	if (ret < 0) {
> +		dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
> +		return ret;
> +	}
> +
> +	regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
> +	if (val & PHY0SUSPEND) {
> +		/*
> +		 * USB PHY0 is in operation mode already
> +		 * make sure USB PHY 60 MHz UTMI Interface Clock ready
> +		 */
> +		timeout = jiffies + msecs_to_jiffies(200);
> +		while (time_before(jiffies, timeout)) {
> +			regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
> +			if (val & PHY0DEVCKSTB)
> +				return 0;
> +			usleep_range(1000, 1500);
> +		}

You want some readl_poll_timeout version here.

> +	}
> +
> +	/*
> +	 * reset USB PHY0.
> +	 * wait until USB PHY0 60 MHz UTMI Interface Clock ready
> +	 */
> +	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND));
> +	timeout = jiffies + msecs_to_jiffies(200);
> +	while (time_before(jiffies, timeout)) {
> +		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
> +		if (val & PHY0DEVCKSTB)
> +			break;
> +		usleep_range(1000, 1500);
> +	}
> +
> +	/* make USB PHY0 enter operation mode */
> +	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEND);
> +
> +	/* make sure USB PHY 60 MHz UTMI Interface Clock ready */
> +	timeout = jiffies + msecs_to_jiffies(200);
> +	while (time_before(jiffies, timeout)) {
> +		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
> +		if (val & PHY0DEVCKSTB)
> +			return 0;
> +		usleep_range(1000, 1500);
> +	}
> +
> +	dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
> +	ret = -ETIMEDOUT;
> +
> +	clk_disable_unprepare(p_phy->clk);
> +	return ret;
> +}
> +
> +static int ma35_usb_phy_power_off(struct phy *phy)
> +{
> +	struct ma35_usb_phy *p_phy = phy_get_drvdata(phy);
> +
> +	clk_disable_unprepare(p_phy->clk);
> +	return 0;
> +}
> +
> +static const struct phy_ops ma35_usb_phy_ops = {
> +	.power_on = ma35_usb_phy_power_on,
> +	.power_off = ma35_usb_phy_power_off,
> +	.owner = THIS_MODULE,
> +};
> +
> +static int ma35_usb_phy_probe(struct platform_device *pdev)
> +{
> +	struct phy_provider *provider;
> +	struct ma35_usb_phy *p_phy;
> +	const char *clkgate;
> +	struct phy *phy;
> +
> +	p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
> +	if (!p_phy)
> +		return -ENOMEM;
> +
> +	p_phy->dev = &pdev->dev;
> +	platform_set_drvdata(pdev, p_phy);
> +
> +	p_phy->sysreg = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node, "nuvoton,sys");
> +	if (IS_ERR(p_phy->sysreg))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->sysreg),
> +				     "Failed to get SYS registers\n");
> +
> +	/* enable clock */
> +	of_property_read_string(p_phy->dev->of_node, "clock-enable", &clkgate);

There is no such property.

> +	p_phy->clk = devm_clk_get(p_phy->dev, clkgate);

Don't mix styles of variables: you were using pdev->dev but now entirely
different. Stick to pdev->dev.

> +	if (IS_ERR(p_phy->clk))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->clk),

And here again pdev->dev... Bring some consistency, not random coding style.

> +				     "Failed to get usb_phy clock\n");
> +


Best regards,
Krzysztof

Dear Krzysztof,

Thank you for your reply.



On 2024/7/29 下午 03:32, Krzysztof Kozlowski wrote:
> On 29/07/2024 08:15, hpchen0 wrote:
>> Nuvoton MA35 SoCs support DWC2 USB controller.
>> Add the driver to drive the USB 2.0 PHY transceivers.
>>
>> Signed-off-by: hpchen0 <hpchen0nvt@gmail.com>
>> +
>> +	ret = clk_prepare_enable(p_phy->clk);
>> +	if (ret < 0) {
>> +		dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
>> +	if (val & PHY0SUSPEND) {
>> +		/*
>> +		 * USB PHY0 is in operation mode already
>> +		 * make sure USB PHY 60 MHz UTMI Interface Clock ready
>> +		 */
>> +		timeout = jiffies + msecs_to_jiffies(200);
>> +		while (time_before(jiffies, timeout)) {
>> +			regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
>> +			if (val & PHY0DEVCKSTB)
>> +				return 0;
>> +			usleep_range(1000, 1500);
>> +		}
> You want some readl_poll_timeout version here.

Okay. The readl_poll_timeout function will be used instead.



>> +	}
>> +
>> +	/*
>> +	 * reset USB PHY0.
>> +	 * wait until USB PHY0 60 MHz UTMI Interface Clock ready
>> +	 */
>> +	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND));
>> +	timeout = jiffies + msecs_to_jiffies(200);
>> +	while (time_before(jiffies, timeout)) {
>> +		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
>> +		if (val & PHY0DEVCKSTB)
>> +			break;
>> +		usleep_range(1000, 1500);
>> +	}
>> +
>> +	/* make USB PHY0 enter operation mode */
>> +	regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEND);
>> +
>> +	/* make sure USB PHY 60 MHz UTMI Interface Clock ready */
>> +	timeout = jiffies + msecs_to_jiffies(200);
>> +	while (time_before(jiffies, timeout)) {
>> +		regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val);
>> +		if (val & PHY0DEVCKSTB)
>> +			return 0;
>> +		usleep_range(1000, 1500);
>> +	}
>> +
>> +	dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
>> +	ret = -ETIMEDOUT;
>> +
>> +	clk_disable_unprepare(p_phy->clk);
>> +	return ret;
>> +}
>> +
>> +static int ma35_usb_phy_power_off(struct phy *phy)
>> +{
>> +	struct ma35_usb_phy *p_phy = phy_get_drvdata(phy);
>> +
>> +	clk_disable_unprepare(p_phy->clk);
>> +	return 0;
>> +}
>> +
>> +static const struct phy_ops ma35_usb_phy_ops = {
>> +	.power_on = ma35_usb_phy_power_on,
>> +	.power_off = ma35_usb_phy_power_off,
>> +	.owner = THIS_MODULE,
>> +};
>> +
>> +static int ma35_usb_phy_probe(struct platform_device *pdev)
>> +{
>> +	struct phy_provider *provider;
>> +	struct ma35_usb_phy *p_phy;
>> +	const char *clkgate;
>> +	struct phy *phy;
>> +
>> +	p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
>> +	if (!p_phy)
>> +		return -ENOMEM;
>> +
>> +	p_phy->dev = &pdev->dev;
>> +	platform_set_drvdata(pdev, p_phy);
>> +
>> +	p_phy->sysreg = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node, "nuvoton,sys");
>> +	if (IS_ERR(p_phy->sysreg))
>> +		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->sysreg),
>> +				     "Failed to get SYS registers\n");
>> +
>> +	/* enable clock */
>> +	of_property_read_string(p_phy->dev->of_node, "clock-enable", &clkgate);
> There is no such property.

I'm sorry, I forgot to remove this part. I will remove it and correct it.



>> +	p_phy->clk = devm_clk_get(p_phy->dev, clkgate);
> Don't mix styles of variables: you were using pdev->dev but now entirely
> different. Stick to pdev->dev.

Okay. I will consistently  use pdev->dev|.|

Thank you for the reminder.



>> +	if (IS_ERR(p_phy->clk))
>> +		return dev_err_probe(&pdev->dev, PTR_ERR(p_phy->clk),
> And here again pdev->dev... Bring some consistency, not random coding style.

Okay. I will consistently  use pdev->dev|.|

Thank you for the reminder.



>> +				     "Failed to get usb_phy clock\n");
>> +
>
> Best regards,
> Krzysztof


Best regards,

Hui-Ping Chen