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[PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes

Prabhakar posted 5 patches 1 year, 4 months ago
There is a newer version of this series
[PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes
Posted by Prabhakar 1 year, 4 months ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
and the GICR is 128kB per CPU.

Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi   | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index d3838e5820fc..c9b9b60a3a36 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
-			reg = <0x0 0x11900000 0 0x40000>,
-			      <0x0 0x11940000 0 0x60000>;
+			reg = <0x0 0x11900000 0 0x20000>,
+			      <0x0 0x11940000 0 0x40000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
index 9cf27ca9f1d2..6f4d4dc13f50 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
@@ -16,3 +16,8 @@ cpus {
 		/delete-node/ cpu@100;
 	};
 };
+
+&gic {
+	reg = <0x0 0x11900000 0 0x20000>,
+	      <0x0 0x11940000 0 0x20000>;
+};
-- 
2.34.1
Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes
Posted by Geert Uytterhoeven 1 year, 4 months ago 
Hi Prabhakar,

On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> and the GICR is 128kB per CPU.
>
> Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
>                         #interrupt-cells = <3>;
>                         #address-cells = <0>;
>                         interrupt-controller;
> -                       reg = <0x0 0x11900000 0 0x40000>,
> -                             <0x0 0x11940000 0 0x60000>;
> +                       reg = <0x0 0x11900000 0 0x20000>,
> +                             <0x0 0x11940000 0 0x40000>;
>                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>                 };
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> index 9cf27ca9f1d2..6f4d4dc13f50 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> @@ -16,3 +16,8 @@ cpus {
>                 /delete-node/ cpu@100;
>         };
>  };
> +
> +&gic {
> +       reg = <0x0 0x11900000 0 0x20000>,
> +             <0x0 0x11940000 0 0x20000>;
> +};

What's the point of overriding this here?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes
Posted by Lad, Prabhakar 1 year, 4 months ago 
Hi Geert,

On Thu, Jul 25, 2024 at 3:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> > and the GICR is 128kB per CPU.
> >
> > Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
> >                         #interrupt-cells = <3>;
> >                         #address-cells = <0>;
> >                         interrupt-controller;
> > -                       reg = <0x0 0x11900000 0 0x40000>,
> > -                             <0x0 0x11940000 0 0x60000>;
> > +                       reg = <0x0 0x11900000 0 0x20000>,
> > +                             <0x0 0x11940000 0 0x40000>;
> >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> >                 };
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > index 9cf27ca9f1d2..6f4d4dc13f50 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > @@ -16,3 +16,8 @@ cpus {
> >                 /delete-node/ cpu@100;
> >         };
> >  };
> > +
> > +&gic {
> > +       reg = <0x0 0x11900000 0 0x20000>,
> > +             <0x0 0x11940000 0 0x20000>;
> > +};
>
> What's the point of overriding this here?
>
Are you suggesting we drop this, as we have no users for it currently?

Cheers,
Prabhakar
Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes
Posted by Geert Uytterhoeven 1 year, 4 months ago 
Hi Prabhakar,

On Thu, Jul 25, 2024 at 4:59 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Jul 25, 2024 at 3:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> > > and the GICR is 128kB per CPU.
> > >
> > > Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > @@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
> > >                         #interrupt-cells = <3>;
> > >                         #address-cells = <0>;
> > >                         interrupt-controller;
> > > -                       reg = <0x0 0x11900000 0 0x40000>,
> > > -                             <0x0 0x11940000 0 0x60000>;
> > > +                       reg = <0x0 0x11900000 0 0x20000>,
> > > +                             <0x0 0x11940000 0 0x40000>;
> > >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > >                 };
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > index 9cf27ca9f1d2..6f4d4dc13f50 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > @@ -16,3 +16,8 @@ cpus {
> > >                 /delete-node/ cpu@100;
> > >         };
> > >  };
> > > +
> > > +&gic {
> > > +       reg = <0x0 0x11900000 0 0x20000>,
> > > +             <0x0 0x11940000 0 0x20000>;
> > > +};
> >
> > What's the point of overriding this here?
> >
> Are you suggesting we drop this, as we have no users for it currently?

I didn't mean to drop it because we have no users of r9a07g044l1.dtsi.
I am just wondering what would be the side-effect of not overriding it?
After all, all r9a07g044 SoC variants have the same GIC hardware block?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes
Posted by Lad, Prabhakar 1 year, 4 months ago 
Hi Geert,

On Thu, Jul 25, 2024 at 4:07 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 25, 2024 at 4:59 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jul 25, 2024 at 3:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> > > > and the GICR is 128kB per CPU.
> > > >
> > > > Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > @@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
> > > >                         #interrupt-cells = <3>;
> > > >                         #address-cells = <0>;
> > > >                         interrupt-controller;
> > > > -                       reg = <0x0 0x11900000 0 0x40000>,
> > > > -                             <0x0 0x11940000 0 0x60000>;
> > > > +                       reg = <0x0 0x11900000 0 0x20000>,
> > > > +                             <0x0 0x11940000 0 0x40000>;
> > > >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > > >                 };
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > index 9cf27ca9f1d2..6f4d4dc13f50 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > @@ -16,3 +16,8 @@ cpus {
> > > >                 /delete-node/ cpu@100;
> > > >         };
> > > >  };
> > > > +
> > > > +&gic {
> > > > +       reg = <0x0 0x11900000 0 0x20000>,
> > > > +             <0x0 0x11940000 0 0x20000>;
> > > > +};
> > >
> > > What's the point of overriding this here?
> > >
> > Are you suggesting we drop this, as we have no users for it currently?
>
> I didn't mean to drop it because we have no users of r9a07g044l1.dtsi.
> I am just wondering what would be the side-effect of not overriding it?
Not sure what side-effects we would see, maybe the IRQ maintainers can
comment on it.

> After all, all r9a07g044 SoC variants have the same GIC hardware block?
>
I would assume so, I dont have a r9a07g044l1 SoC to verify it. Maybe I
will drop this until it's verified.

Cheers,
Prabhakar

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