arch/arm64/boot/dts/freescale/s32g2.dtsi | 51 +++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 53 +++++++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-)
Add the pinctrl node in the device tree in order to enable the
S32G2/S32G3 pinctrl driver to probe.
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 51 +++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 53 +++++++++++++++++++++++-
2 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fc19ae2e8d3b..b31f6857640b 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -159,5 +159,56 @@ gic: interrupt-controller@50800000 {
interrupt-controller;
#interrupt-cells = <3>;
};
+
+ pinctrl: pinctrl@4009c240 {
+ compatible = "nxp,s32g2-siul2-pinctrl";
+ /* MSCR0-MSCR101 registers on siul2_0 */
+ reg = <0x4009c240 0x198>,
+ /* MSCR112-MSCR122 registers on siul2_1 */
+ <0x44010400 0x2c>,
+ /* MSCR144-MSCR190 registers on siul2_1 */
+ <0x44010480 0xbc>,
+ /* IMCR0-IMCR83 registers on siul2_0 */
+ <0x4009ca40 0x150>,
+ /* IMCR119-IMCR397 registers on siul2_1 */
+ <0x44010c1c 0x45c>,
+ /* IMCR430-IMCR495 registers on siul2_1 */
+ <0x440110f8 0x108>;
+ status = "okay";
+
+ jtag_pins: jtag_pins {
+ jtag_grp0 {
+ pinmux = <0x0>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+
+ jtag_grp1 {
+ pinmux = <0x11>;
+ slew-rate = <166>;
+ };
+
+ jtag_grp2 {
+ pinmux = <0x40>;
+ input-enable;
+ bias-pull-down;
+ slew-rate = <166>;
+ };
+
+ jtag_grp3 {
+ pinmux = <0x23c0>,
+ <0x23d0>,
+ <0x2320>;
+ };
+
+ jtag_grp4 {
+ pinmux = <0x51>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index c1b08992754b..7a8c6c943706 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2023 NXP
+ * Copyright 2021-2024 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -218,6 +218,57 @@ gic: interrupt-controller@50800000 {
<0x50420000 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pinctrl: pinctrl@4009c240 {
+ compatible = "nxp,s32g2-siul2-pinctrl";
+ /* MSCR0-MSCR101 registers on siul2_0 */
+ reg = <0x4009c240 0x198>,
+ /* MSCR112-MSCR122 registers on siul2_1 */
+ <0x44010400 0x2c>,
+ /* MSCR144-MSCR190 registers on siul2_1 */
+ <0x44010480 0xbc>,
+ /* IMCR0-IMCR83 registers on siul2_0 */
+ <0x4009ca40 0x150>,
+ /* IMCR119-IMCR397 registers on siul2_1 */
+ <0x44010c1c 0x45c>,
+ /* IMCR430-IMCR495 registers on siul2_1 */
+ <0x440110f8 0x108>;
+ status = "okay";
+
+ jtag_pins: jtag_pins {
+ jtag_grp0 {
+ pinmux = <0x0>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+
+ jtag_grp1 {
+ pinmux = <0x11>;
+ slew-rate = <166>;
+ };
+
+ jtag_grp2 {
+ pinmux = <0x40>;
+ input-enable;
+ bias-pull-down;
+ slew-rate = <166>;
+ };
+
+ jtag_grp3 {
+ pinmux = <0x23c0>,
+ <0x23d0>,
+ <0x2320>;
+ };
+
+ jtag_grp4 {
+ pinmux = <0x51>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+ };
+ };
};
timer {
--
2.45.2
On 23/07/2024 14:37, Andrei Stefanescu wrote: > Add the pinctrl node in the device tree in order to enable the > S32G2/S32G3 pinctrl driver to probe. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> > --- > arch/arm64/boot/dts/freescale/s32g2.dtsi | 51 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/s32g3.dtsi | 53 +++++++++++++++++++++++- > 2 files changed, 103 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi > index fc19ae2e8d3b..b31f6857640b 100644 > --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi > @@ -159,5 +159,56 @@ gic: interrupt-controller@50800000 { > interrupt-controller; > #interrupt-cells = <3>; > }; > + > + pinctrl: pinctrl@4009c240 { > + compatible = "nxp,s32g2-siul2-pinctrl"; > + /* MSCR0-MSCR101 registers on siul2_0 */ > + reg = <0x4009c240 0x198>, > + /* MSCR112-MSCR122 registers on siul2_1 */ > + <0x44010400 0x2c>, > + /* MSCR144-MSCR190 registers on siul2_1 */ > + <0x44010480 0xbc>, > + /* IMCR0-IMCR83 registers on siul2_0 */ > + <0x4009ca40 0x150>, > + /* IMCR119-IMCR397 registers on siul2_1 */ > + <0x44010c1c 0x45c>, > + /* IMCR430-IMCR495 registers on siul2_1 */ > + <0x440110f8 0x108>; > + status = "okay"; Where did you disable it? > + > + jtag_pins: jtag_pins { Underscores are not allowed. Please follow DTS coding style. The mainline one, not NXP coding style. Several other places here have also issues, so be sure you read if carefully. > timer { Best regards, Krzysztof
Hi Krzysztof, Thank you for the prompt review! On 23/07/2024 16:38, Krzysztof Kozlowski wrote: > On 23/07/2024 14:37, Andrei Stefanescu wrote: >> + status = "okay"; > > Where did you disable it? It isn't disabled anywhere. I thought we should always have it enabled since most of the other drivers will rely on it. Should I add it here disabled and enable it in the board specific .dts files (in this case: s32g399a-rdb3.dts, s32g274a-rdb2.dts and s32g274a-evb.dts)? > >> + >> + jtag_pins: jtag_pins { > > Underscores are not allowed. Please follow DTS coding style. The > mainline one, not NXP coding style. Several other places here have also > issues, so be sure you read if carefully. Thank you! I will send a V2 with "jtag_pins: jtag-pins {" and all the other subnodes renamed to "jtag-grp*". > >> timer { > > Best regards, > Krzysztof > Best regards, Andrei
On 23/07/2024 15:56, Andrei Stefanescu wrote: > Hi Krzysztof, > > Thank you for the prompt review! > > On 23/07/2024 16:38, Krzysztof Kozlowski wrote: >> On 23/07/2024 14:37, Andrei Stefanescu wrote: >>> + status = "okay"; >> >> Where did you disable it? > > It isn't disabled anywhere. Then what is the point of enabling if it is not disabled? > I thought we should always have it enabled since most of the > other drivers will rely on it. Should I add it here disabled and enable it in the > board specific .dts files (in this case: s32g399a-rdb3.dts, s32g274a-rdb2.dts and > s32g274a-evb.dts)? No. I think coding style covers it, please read it. > >> >>> + >>> + jtag_pins: jtag_pins { >> >> Underscores are not allowed. Please follow DTS coding style. The >> mainline one, not NXP coding style. Several other places here have also >> issues, so be sure you read if carefully. > > Thank you! I will send a V2 with "jtag_pins: jtag-pins {" and > all the other subnodes renamed to "jtag-grp*". Well, fix also other coding style violations... Best regards, Krzysztof
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