From: Yann Sionneau <ysionneau@kalrayinc.com>
Add binding for Kalray Coolidge APIC GIC interrupt controller.
Co-developed-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Jules Maselbas <jmaselbas@zdiv.net>
Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com>
---
Notes:
V2 -> V3: Fixed bindings to adhere to dt-schema
---
.../kalray,coolidge-apic-gic.yaml | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
new file mode 100644
index 0000000000000..02e25256c1c1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,coolidge-apic-gic.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/kalray,coolidge-apic-gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kalray kv3-1 APIC-GIC
+
+maintainers:
+ - Jonathan Borne <jborne@kalrayinc.com>
+ - Julian Vetter <jvetter@kalrayinc.com>
+ - Yann Sionneau <ysionneau@kalrayinc.com>
+
+description: |
+ Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt
+ Controller (APIC) which is split in two part:
+ - a Generic Interrupt Controller (referred as APIC-GIC)
+ - a Mailbox Controller (referred as APIC-Mailbox)
+ The APIC-GIC acts as an intermediary interrupt controller, muxing/routing
+ incoming interrupts to output interrupts connected to kvx cores interrupts lines.
+ The 139 possible input interrupt lines are organized as follow:
+ - 128 from the mailbox controller (one it per mailboxes)
+ - 1 from the NoC router
+ - 5 from IOMMUs
+ - 1 from L2 cache DMA job FIFO
+ - 1 from cluster watchdog
+ - 2 for SECC, DECC
+ - 1 from Data NoC
+ The 72 possible output interrupt lines:
+ - 68 : 4 interrupts per cores (17 cores)
+ - 1 for L2 cache controller
+ - 3 extra that are for padding
+
+properties:
+ compatible:
+ const: kalray,coolidge-apic-gic
+
+ reg:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 1
+ description: The IRQ number.
+
+ interrupt-controller: true
+
+ interrupts-extended:
+ maxItems: 16
+ description: |
+ Specifies the interrupt line(s) in the interrupt-parent controller node;
+ valid values depend on the type of parent interrupt controller
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - interrupt-controller
+ - interrupts-extended
+
+additionalProperties: false
+
+examples:
+ - |
+ apic_gic: interrupt-controller@a20000 {
+ compatible = "kalray,coolidge-apic-gic";
+ reg = <0 0xa20000 0 0x12000>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&core_intc0 0x4>,
+ <&core_intc1 0x4>,
+ <&core_intc2 0x4>,
+ <&core_intc3 0x4>,
+ <&core_intc4 0x4>,
+ <&core_intc5 0x4>,
+ <&core_intc6 0x4>,
+ <&core_intc7 0x4>,
+ <&core_intc8 0x4>,
+ <&core_intc9 0x4>,
+ <&core_intc10 0x4>,
+ <&core_intc11 0x4>,
+ <&core_intc12 0x4>,
+ <&core_intc13 0x4>,
+ <&core_intc14 0x4>,
+ <&core_intc15 0x4>;
+ };
+
+...
--
2.45.2