From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
We are using devres APIs for divider, mux and pll5 clocks so for
consistency use the devres APIs for module, fixed factor and PLL clocks.
While at it switched to clk_hw_register() instead of clk_register()
as this has been marked as deprecated interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- Propagate error code from rzg2l_cpg_pll_clk_register() if
devm_clk_hw_register() fails
- Used devm_clk_hw_register_fixed_factor() for fixed factor clock
- Set error pointer in rzg2l_cpg_register_mod_clk() if
devm_clk_hw_register() failed
---
drivers/clk/renesas/rzg2l-cpg.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 04b78064d4e0..1fe71a18cf86 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1023,6 +1023,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
struct clk_init_data init;
const char *parent_name;
struct pll_clk *pll_clk;
+ int ret;
parent = clks[core->parent & 0xffff];
if (IS_ERR(parent))
@@ -1045,7 +1046,11 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
pll_clk->priv = priv;
pll_clk->type = core->type;
- return clk_register(NULL, &pll_clk->hw);
+ ret = devm_clk_hw_register(dev, &pll_clk->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return pll_clk->hw.clk;
}
static struct clk
@@ -1116,6 +1121,8 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
break;
case CLK_TYPE_FF:
+ struct clk_hw *clk_hw;
+
WARN_DEBUG(core->parent >= priv->num_core_clks);
parent = priv->clks[core->parent];
if (IS_ERR(parent)) {
@@ -1124,9 +1131,13 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
}
parent_name = __clk_get_name(parent);
- clk = clk_register_fixed_factor(NULL, core->name,
- parent_name, CLK_SET_RATE_PARENT,
- core->mult, div);
+ clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name, parent_name,
+ CLK_SET_RATE_PARENT,
+ core->mult, div);
+ if (IS_ERR(clk_hw))
+ clk = ERR_CAST(clk_hw);
+ else
+ clk = clk_hw->clk;
break;
case CLK_TYPE_SAM_PLL:
clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
@@ -1337,6 +1348,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
struct clk *parent, *clk;
const char *parent_name;
unsigned int i;
+ int ret;
WARN_DEBUG(id < priv->num_core_clks);
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
@@ -1380,10 +1392,13 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
clock->priv = priv;
clock->hw.init = &init;
- clk = clk_register(NULL, &clock->hw);
- if (IS_ERR(clk))
+ ret = devm_clk_hw_register(dev, &clock->hw);
+ if (ret) {
+ clk = ERR_PTR(ret);
goto fail;
+ }
+ clk = clock->hw.clk;
dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
priv->clks[id] = clk;
--
2.34.1Hi Prabhakar,
On Mon, Jul 15, 2024 at 12:37 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> We are using devres APIs for divider, mux and pll5 clocks so for
> consistency use the devres APIs for module, fixed factor and PLL clocks.
>
> While at it switched to clk_hw_register() instead of clk_register()
> as this has been marked as deprecated interface.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Propagate error code from rzg2l_cpg_pll_clk_register() if
> devm_clk_hw_register() fails
> - Used devm_clk_hw_register_fixed_factor() for fixed factor clock
> - Set error pointer in rzg2l_cpg_register_mod_clk() if
> devm_clk_hw_register() failed
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1116,6 +1121,8 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
> clk = of_clk_get_by_name(priv->dev->of_node, core->name);
> break;
> case CLK_TYPE_FF:
> + struct clk_hw *clk_hw;
I will move this up while applying, to match the style of the rest of
the file.
> +
> WARN_DEBUG(core->parent >= priv->num_core_clks);
> parent = priv->clks[core->parent];
> if (IS_ERR(parent)) {
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.12.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert, Thank you for the review. On Fri, Jul 26, 2024 at 4:09 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Jul 15, 2024 at 12:37 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > We are using devres APIs for divider, mux and pll5 clocks so for > > consistency use the devres APIs for module, fixed factor and PLL clocks. > > > > While at it switched to clk_hw_register() instead of clk_register() > > as this has been marked as deprecated interface. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > - Propagate error code from rzg2l_cpg_pll_clk_register() if > > devm_clk_hw_register() fails > > - Used devm_clk_hw_register_fixed_factor() for fixed factor clock > > - Set error pointer in rzg2l_cpg_register_mod_clk() if > > devm_clk_hw_register() failed > > Thanks for the update! > > > --- a/drivers/clk/renesas/rzg2l-cpg.c > > +++ b/drivers/clk/renesas/rzg2l-cpg.c > > @@ -1116,6 +1121,8 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, > > clk = of_clk_get_by_name(priv->dev->of_node, core->name); > > break; > > case CLK_TYPE_FF: > > + struct clk_hw *clk_hw; > > I will move this up while applying, to match the style of the rest of > the file. > Good point, thanks for taking care of it. Cheers, Prabhakar
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