The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
mark the APPS and PCIE ones as well.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23f1b2e5e624..95691ab58a23 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3070,6 +3070,7 @@
 			reg = <0x0 0x15000000 0x0 0x100000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <2>;
+			dma-coherent;
 
 			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@@ -3208,6 +3209,7 @@
 			reg = <0x0 0x15200000 0x0 0x80000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <2>;
+			dma-coherent;
 
 			interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.17.1

On Mon, Jul 15, 2024 at 12:46:49PM GMT, Qingqing Zhou wrote:
> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
> mark the APPS and PCIE ones as well.
> 
> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>

I think this deserves a Fixes tag as well, not treating it as
dma-coherent is a bug and can lead to difficult to debug errors based on
a quick search through lkml.

Thanks,
Andrew

在 7/16/2024 2:14 AM, Andrew Halaney 写道:
> On Mon, Jul 15, 2024 at 12:46:49PM GMT, Qingqing Zhou wrote:
>> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
>> mark the APPS and PCIE ones as well.
>>
>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> 
> I think this deserves a Fixes tag as well, not treating it as
> dma-coherent is a bug and can lead to difficult to debug errors based on
> a quick search through lkml.
> 
> Thanks,
> Andrew
> 

Andrew, thanks for your review comments, do you mean to add below two lines?
Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")

Thanks,
Qingqing

On Tue, Jul 16, 2024 at 02:00:15PM +0800, Qingqing Zhou wrote:
> 
> 
> 在 7/16/2024 2:14 AM, Andrew Halaney 写道:
> > On Mon, Jul 15, 2024 at 12:46:49PM GMT, Qingqing Zhou wrote:
> >> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
> >> mark the APPS and PCIE ones as well.
> >>
> >> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
> > 
> > I think this deserves a Fixes tag as well, not treating it as
> > dma-coherent is a bug and can lead to difficult to debug errors based on
> > a quick search through lkml.
> > 
> > Thanks,
> > Andrew
> > 
> 
> Andrew, thanks for your review comments, do you mean to add below two lines?
> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
> Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
> 

Yes, looks to be it. With the tags added,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

And CC stable if the offending commits went into any stable kernels.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Hi Mani,
Thanks for reviewing, do you mean to post a new patch which adds "Fixes:" tags and "cc: stable@vger.kernel.org"?

在 7/16/2024 2:05 PM, Manivannan Sadhasivam 写道:
> On Tue, Jul 16, 2024 at 02:00:15PM +0800, Qingqing Zhou wrote:
>>
>>
>> 在 7/16/2024 2:14 AM, Andrew Halaney 写道:
>>> On Mon, Jul 15, 2024 at 12:46:49PM GMT, Qingqing Zhou wrote:
>>>> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
>>>> mark the APPS and PCIE ones as well.
>>>>
>>>> Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
>>>
>>> I think this deserves a Fixes tag as well, not treating it as
>>> dma-coherent is a bug and can lead to difficult to debug errors based on
>>> a quick search through lkml.
>>>
>>> Thanks,
>>> Andrew
>>>
>>
>> Andrew, thanks for your review comments, do you mean to add below two lines?
>> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
>> Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
>>
> 
> Yes, looks to be it. With the tags added,
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> And CC stable if the offending commits went into any stable kernels.
> 
> - Mani
> 

On 15.07.2024 9:16 AM, Qingqing Zhou wrote:
> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
> mark the APPS and PCIE ones as well.

Please double-check what you copy-paste, there's no PCIe SMMU in this
patch

Looks good otherwise

Konrad

On 15.07.2024 6:39 PM, Konrad Dybcio wrote:
> On 15.07.2024 9:16 AM, Qingqing Zhou wrote:
>> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
>> mark the APPS and PCIE ones as well.
> 
> Please double-check what you copy-paste, there's no PCIe SMMU in this
> patch
> 
> Looks good otherwise

Konrad, please double check what you say to people on lkml.. sorry bout that..


Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad