The aligned pages for cache invalidation returned by
calculate_psi_aligned_address() are incorrect if the start pfn is not
aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
uses the number of pages to flush caches for the first-stage
translation.

Fix this by updating the aligned pages once the address mask is adjusted.

Change log:

v2:
 - Add a new fix to Limit max address mask to MAX_AGAW_PFN_WIDTH.

v1: https://lore.kernel.org/linux-iommu/20240708121417.18705-1-baolu.lu@linux.intel.com/

Lu Baolu (2):
  iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
  iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()

 drivers/iommu/intel/cache.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.34.1

On Tue, 09 Jul 2024 23:26:41 +0800, Lu Baolu wrote:
> The aligned pages for cache invalidation returned by
> calculate_psi_aligned_address() are incorrect if the start pfn is not
> aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
> uses the number of pages to flush caches for the first-stage
> translation.
> 
> Fix this by updating the aligned pages once the address mask is adjusted.
> 
> [...]

Applied to iommu (intel/vt-d), thanks!

[1/2] iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
      https://git.kernel.org/iommu/c/c420a2b4e8be
[2/2] iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()
      https://git.kernel.org/iommu/c/0a3f6b346301

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
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