.../phy/hisilicon,hi3798cv200-combphy.yaml | 57 ++++++++++++++++++ .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 ------------------- 2 files changed, 57 insertions(+), 59 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
Convert the hisilicon,hi3798cv200-combphy binding to DT schema format.
Drop the example as arm/hisilicon/controller/hi3798cv200-perictrl.yaml
already contains an example of this binding.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
.../phy/hisilicon,hi3798cv200-combphy.yaml | 57 ++++++++++++++++++
.../bindings/phy/phy-hi3798cv200-combphy.txt | 59 -------------------
2 files changed, 57 insertions(+), 59 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
diff --git a/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml b/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml
new file mode 100644
index 000000000000..814504492f30
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon STB PCIE/SATA/USB3 PHY
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+ - Jianguo Sun <sunjianguo1@huawei.com>
+
+properties:
+ compatible:
+ const: hisilicon,hi3798cv200-combphy
+
+ reg:
+ maxItems: 1
+
+ '#phy-cells':
+ description: The cell contains the PHY mode
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ hisilicon,fixed-mode:
+ description: If the phy device doesn't support mode select but a fixed mode
+ setting, the property should be present to specify the particular mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 4] # SATA, PCIE, USB3
+
+ hisilicon,mode-select-bits:
+ description: If the phy device support mode select, this property should be
+ present to specify the register bits in peripheral controller.
+ items:
+ - description: register_offset
+ - description: bit shift
+ - description: bit mask
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+ - resets
+
+oneOf:
+ - required: ['hisilicon,fixed-mode']
+ - required: ['hisilicon,mode-select-bits']
+
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
deleted file mode 100644
index 17b0c761370a..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-HiSilicon STB PCIE/SATA/USB3 PHY
-
-Required properties:
-- compatible: Should be "hisilicon,hi3798cv200-combphy"
-- reg: Should be the address space for COMBPHY configuration and state
- registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
- PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
-- #phy-cells: Should be 1. The cell number is used to select the phy mode
- as defined in <dt-bindings/phy/phy.h>.
-- clocks: The phandle to clock provider and clock specifier pair.
-- resets: The phandle to reset controller and reset specifier pair.
-
-Refer to phy/phy-bindings.txt for the generic PHY binding properties.
-
-Optional properties:
-- hisilicon,fixed-mode: If the phy device doesn't support mode select
- but a fixed mode setting, the property should be present to specify
- the particular mode.
-- hisilicon,mode-select-bits: If the phy device support mode select,
- this property should be present to specify the register bits in
- peripheral controller, as a 3 integers tuple:
- <register_offset bit_shift bit_mask>.
-
-Notes:
-- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
- one of them should be present.
-- The device node should be a child of peripheral controller that contains
- COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
- Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
- bindings.
-
-Examples:
-
-perictrl: peripheral-controller@8a20000 {
- compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
- "simple-mfd";
- reg = <0x8a20000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8a20000 0x1000>;
-
- combphy0: phy@850 {
- compatible = "hisilicon,hi3798cv200-combphy";
- reg = <0x850 0x8>;
- #phy-cells = <1>;
- clocks = <&crg HISTB_COMBPHY0_CLK>;
- resets = <&crg 0x188 4>;
- hisilicon,fixed-mode = <PHY_TYPE_USB3>;
- };
-
- combphy1: phy@858 {
- compatible = "hisilicon,hi3798cv200-combphy";
- reg = <0x858 0x8>;
- #phy-cells = <1>;
- clocks = <&crg HISTB_COMBPHY1_CLK>;
- resets = <&crg 0x188 12>;
- hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
- };
-};
--
2.43.0
On Wed, 03 Jul 2024 15:59:04 -0600, Rob Herring (Arm) wrote:
> Convert the hisilicon,hi3798cv200-combphy binding to DT schema format.
>
> Drop the example as arm/hisilicon/controller/hi3798cv200-perictrl.yaml
> already contains an example of this binding.
>
>
Applied, thanks!
[1/1] dt-bindings: phy: hisilicon,hi3798cv200-combphy: Convert to DT schema
commit: dd1051f9329880a0749954e601a5ece9a07f8685
Best regards,
--
Vinod Koul <vkoul@kernel.org>
On Thu, Jul 4, 2024 at 5:59 AM Rob Herring (Arm) <robh@kernel.org> wrote: > > Convert the hisilicon,hi3798cv200-combphy binding to DT schema format. > > Drop the example as arm/hisilicon/controller/hi3798cv200-perictrl.yaml > already contains an example of this binding. > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Shawn Guo <shawn.guo@linaro.org>
On Wed, Jul 3, 2024 at 3:59 PM Rob Herring (Arm) <robh@kernel.org> wrote: > > Convert the hisilicon,hi3798cv200-combphy binding to DT schema format. > > Drop the example as arm/hisilicon/controller/hi3798cv200-perictrl.yaml > already contains an example of this binding. > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org> > --- > .../phy/hisilicon,hi3798cv200-combphy.yaml | 57 ++++++++++++++++++ > .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 ------------------- > 2 files changed, 57 insertions(+), 59 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml > delete mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt > > diff --git a/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml b/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml > new file mode 100644 > index 000000000000..814504492f30 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: HiSilicon STB PCIE/SATA/USB3 PHY > + > +maintainers: > + - Shawn Guo <shawn.guo@linaro.org> > + - Jianguo Sun <sunjianguo1@huawei.com> And this bounces, so I guess Shawn is stuck with it... Rob
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