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[PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops

Satya Priya Kakitapalli posted 6 patches 1 year, 5 months ago
[PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Satya Priya Kakitapalli 1 year, 5 months ago 
From: Taniya Das <quic_tdas@quicinc.com>

Regera PLL ops are required to control the Regera PLL from clock
controller drivers, thus add support for the same.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/clk/qcom/clk-alpha-pll.c | 32 +++++++++++++++++++++++++++++++-
 drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index d2bef078588f..afb7ab72c90d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -2605,3 +2605,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
 	.set_rate = clk_alpha_pll_stromer_plus_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
+
+void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+			     const struct alpha_pll_config *config)
+{
+	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
+	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
+	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
+	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
+	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
+	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
+	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
+
+	/* Set operation mode to STANDBY */
+	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
+}
+EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
+
+const struct clk_ops clk_alpha_pll_regera_ops = {
+	.enable = clk_zonda_pll_enable,
+	.disable = clk_zonda_pll_disable,
+	.is_enabled = clk_alpha_pll_is_enabled,
+	.recalc_rate = clk_trion_pll_recalc_rate,
+	.round_rate = clk_alpha_pll_round_rate,
+	.set_rate = clk_zonda_pll_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index fb6d50263bb9..5bb0a07da53d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -21,6 +21,7 @@ enum {
 	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
 	CLK_ALPHA_PLL_TYPE_AGERA,
 	CLK_ALPHA_PLL_TYPE_ZONDA,
+	CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
 	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
 	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
 	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
@@ -189,6 +190,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
 
+extern const struct clk_ops clk_alpha_pll_regera_ops;
+
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -210,5 +213,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
 				  const struct alpha_pll_config *config);
 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			       const struct alpha_pll_config *config);
+void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+			     const struct alpha_pll_config *config);
 
 #endif

-- 
2.25.1
Re: [PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Dmitry Baryshkov 1 year, 5 months ago 
On Tue, Jul 02, 2024 at 09:20:41PM GMT, Satya Priya Kakitapalli wrote:
> From: Taniya Das <quic_tdas@quicinc.com>
> 
> Regera PLL ops are required to control the Regera PLL from clock
> controller drivers, thus add support for the same.

the same what?

> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 32 +++++++++++++++++++++++++++++++-
>  drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
>  2 files changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index d2bef078588f..afb7ab72c90d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
> - * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
>  #include <linux/kernel.h>
> @@ -2605,3 +2605,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
>  	.set_rate = clk_alpha_pll_stromer_plus_set_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
> +
> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> +			     const struct alpha_pll_config *config)
> +{
> +	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
> +	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
> +
> +	/* Set operation mode to STANDBY */
> +	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +}
> +EXPORT_SYMBOL_GPL(clk_regera_pll_configure);

Does it make sense to call this function from clk_zonda_pll_configure()?

> +
> +const struct clk_ops clk_alpha_pll_regera_ops = {
> +	.enable = clk_zonda_pll_enable,
> +	.disable = clk_zonda_pll_disable,
> +	.is_enabled = clk_alpha_pll_is_enabled,
> +	.recalc_rate = clk_trion_pll_recalc_rate,
> +	.round_rate = clk_alpha_pll_round_rate,
> +	.set_rate = clk_zonda_pll_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index fb6d50263bb9..5bb0a07da53d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -21,6 +21,7 @@ enum {
>  	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
>  	CLK_ALPHA_PLL_TYPE_AGERA,
>  	CLK_ALPHA_PLL_TYPE_ZONDA,
> +	CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
>  	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
>  	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
>  	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
> @@ -189,6 +190,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
>  extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
>  #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
>  
> +extern const struct clk_ops clk_alpha_pll_regera_ops;
> +
>  void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  			     const struct alpha_pll_config *config);
>  void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> @@ -210,5 +213,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
>  				  const struct alpha_pll_config *config);
>  void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  			       const struct alpha_pll_config *config);
> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> +			     const struct alpha_pll_config *config);
>  
>  #endif
> 
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry
Re: [PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Satya Priya Kakitapalli (Temp) 1 year, 5 months ago 
On 7/3/2024 3:35 PM, Dmitry Baryshkov wrote:
> On Tue, Jul 02, 2024 at 09:20:41PM GMT, Satya Priya Kakitapalli wrote:
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Regera PLL ops are required to control the Regera PLL from clock
>> controller drivers, thus add support for the same.
> the same what?


I'll rephrase the commit text.


>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
>>   drivers/clk/qcom/clk-alpha-pll.c | 32 +++++++++++++++++++++++++++++++-
>>   drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
>>   2 files changed, 36 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index d2bef078588f..afb7ab72c90d 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -1,7 +1,7 @@
>>   // SPDX-License-Identifier: GPL-2.0
>>   /*
>>    * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
>> - * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
>>    */
>>   
>>   #include <linux/kernel.h>
>> @@ -2605,3 +2605,33 @@ const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
>>   	.set_rate = clk_alpha_pll_stromer_plus_set_rate,
>>   };
>>   EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
>> +
>> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>> +			     const struct alpha_pll_config *config)
>> +{
>> +	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
>> +	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
>> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
>> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
>> +
>> +	/* Set operation mode to STANDBY */
>> +	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
>> +}
>> +EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
> Does it make sense to call this function from clk_zonda_pll_configure()?


Okay, I'll evaluate this internally and see if that can be done.


>
>> +
>> +const struct clk_ops clk_alpha_pll_regera_ops = {
>> +	.enable = clk_zonda_pll_enable,
>> +	.disable = clk_zonda_pll_disable,
>> +	.is_enabled = clk_alpha_pll_is_enabled,
>> +	.recalc_rate = clk_trion_pll_recalc_rate,
>> +	.round_rate = clk_alpha_pll_round_rate,
>> +	.set_rate = clk_zonda_pll_set_rate,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
>> index fb6d50263bb9..5bb0a07da53d 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.h
>> +++ b/drivers/clk/qcom/clk-alpha-pll.h
>> @@ -21,6 +21,7 @@ enum {
>>   	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
>>   	CLK_ALPHA_PLL_TYPE_AGERA,
>>   	CLK_ALPHA_PLL_TYPE_ZONDA,
>> +	CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
>>   	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
>>   	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
>>   	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
>> @@ -189,6 +190,8 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
>>   extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
>>   #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
>>   
>> +extern const struct clk_ops clk_alpha_pll_regera_ops;
>> +
>>   void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>   			     const struct alpha_pll_config *config);
>>   void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>> @@ -210,5 +213,7 @@ void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
>>   				  const struct alpha_pll_config *config);
>>   void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>   			       const struct alpha_pll_config *config);
>> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>> +			     const struct alpha_pll_config *config);
>>   
>>   #endif
>>
>> -- 
>> 2.25.1
>>
Re: [PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Satya Priya Kakitapalli (Temp) 1 year, 4 months ago 
On 7/9/2024 4:21 PM, Satya Priya Kakitapalli (Temp) wrote:
>
> On 7/3/2024 3:35 PM, Dmitry Baryshkov wrote:
>> On Tue, Jul 02, 2024 at 09:20:41PM GMT, Satya Priya Kakitapalli wrote:
>>> From: Taniya Das <quic_tdas@quicinc.com>
>>>
>>> Regera PLL ops are required to control the Regera PLL from clock
>>> controller drivers, thus add support for the same.
>> the same what?
>
>
> I'll rephrase the commit text.
>
>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>> ---
>>>   drivers/clk/qcom/clk-alpha-pll.c | 32 
>>> +++++++++++++++++++++++++++++++-
>>>   drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
>>>   2 files changed, 36 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c 
>>> b/drivers/clk/qcom/clk-alpha-pll.c
>>> index d2bef078588f..afb7ab72c90d 100644
>>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>>> @@ -1,7 +1,7 @@
>>>   // SPDX-License-Identifier: GPL-2.0
>>>   /*
>>>    * Copyright (c) 2015, 2018, The Linux Foundation. All rights 
>>> reserved.
>>> - * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All 
>>> rights reserved.
>>> + * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. 
>>> All rights reserved.
>>>    */
>>>     #include <linux/kernel.h>
>>> @@ -2605,3 +2605,33 @@ const struct clk_ops 
>>> clk_alpha_pll_stromer_plus_ops = {
>>>       .set_rate = clk_alpha_pll_stromer_plus_set_rate,
>>>   };
>>>   EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
>>> +
>>> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct 
>>> regmap *regmap,
>>> +                 const struct alpha_pll_config *config)
>>> +{
>>> +    clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
>>> +    clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), 
>>> config->alpha);
>>> +    clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 
>>> config->config_ctl_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 
>>> config->config_ctl_hi_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 
>>> config->config_ctl_hi1_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 
>>> config->user_ctl_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 
>>> config->user_ctl_hi_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 
>>> config->user_ctl_hi1_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 
>>> config->test_ctl_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 
>>> config->test_ctl_hi_val);
>>> +    clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 
>>> config->test_ctl_hi1_val);
>>> +
>>> +    /* Set operation mode to STANDBY */
>>> +    regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
>>> +}
>>> +EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
>> Does it make sense to call this function from clk_zonda_pll_configure()?
>
>
> Okay, I'll evaluate this internally and see if that can be done.
>

I have checked this, although there is common part between Zonda and 
Regera PLL configure APIs, a different sequence needs to be followed for 
Zonda, and calling this function from zonda_pll_configure would affect 
the sequence. Hence, I think it is better to leave it as is.


>
>>
>>> +
>>> +const struct clk_ops clk_alpha_pll_regera_ops = {
>>> +    .enable = clk_zonda_pll_enable,
>>> +    .disable = clk_zonda_pll_disable,
>>> +    .is_enabled = clk_alpha_pll_is_enabled,
>>> +    .recalc_rate = clk_trion_pll_recalc_rate,
>>> +    .round_rate = clk_alpha_pll_round_rate,
>>> +    .set_rate = clk_zonda_pll_set_rate,
>>> +};
>>> +EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.h 
>>> b/drivers/clk/qcom/clk-alpha-pll.h
>>> index fb6d50263bb9..5bb0a07da53d 100644
>>> --- a/drivers/clk/qcom/clk-alpha-pll.h
>>> +++ b/drivers/clk/qcom/clk-alpha-pll.h
>>> @@ -21,6 +21,7 @@ enum {
>>>       CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
>>>       CLK_ALPHA_PLL_TYPE_AGERA,
>>>       CLK_ALPHA_PLL_TYPE_ZONDA,
>>> +    CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA,
>>>       CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
>>>       CLK_ALPHA_PLL_TYPE_LUCID_EVO,
>>>       CLK_ALPHA_PLL_TYPE_LUCID_OLE,
>>> @@ -189,6 +190,8 @@ extern const struct clk_ops 
>>> clk_alpha_pll_postdiv_lucid_evo_ops;
>>>   extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
>>>   #define clk_alpha_pll_postdiv_rivian_evo_ops 
>>> clk_alpha_pll_postdiv_fabia_ops
>>>   +extern const struct clk_ops clk_alpha_pll_regera_ops;
>>> +
>>>   void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct 
>>> regmap *regmap,
>>>                    const struct alpha_pll_config *config);
>>>   void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct 
>>> regmap *regmap,
>>> @@ -210,5 +213,7 @@ void clk_rivian_evo_pll_configure(struct 
>>> clk_alpha_pll *pll, struct regmap *regm
>>>                     const struct alpha_pll_config *config);
>>>   void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct 
>>> regmap *regmap,
>>>                      const struct alpha_pll_config *config);
>>> +void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct 
>>> regmap *regmap,
>>> +                 const struct alpha_pll_config *config);
>>>     #endif
>>>
>>> -- 
>>> 2.25.1
>>>
Re: [PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Dmitry Baryshkov 1 year, 4 months ago 
On Fri, Jul 26, 2024 at 01:40:33PM GMT, Satya Priya Kakitapalli (Temp) wrote:
> 
> On 7/9/2024 4:21 PM, Satya Priya Kakitapalli (Temp) wrote:
> > 
> > On 7/3/2024 3:35 PM, Dmitry Baryshkov wrote:
> > > On Tue, Jul 02, 2024 at 09:20:41PM GMT, Satya Priya Kakitapalli wrote:
> > > > From: Taniya Das <quic_tdas@quicinc.com>
> > > > 
> > > > Regera PLL ops are required to control the Regera PLL from clock
> > > > controller drivers, thus add support for the same.
> > > the same what?
> > 
> > 
> > I'll rephrase the commit text.
> > 
> > 
> > > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> > > > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> > > > ---
> > > >   drivers/clk/qcom/clk-alpha-pll.c | 32
> > > > +++++++++++++++++++++++++++++++-
> > > >   drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
> > > >   2 files changed, 36 insertions(+), 1 deletion(-)

[...]

> > > > +EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
> > > Does it make sense to call this function from clk_zonda_pll_configure()?
> > 
> > 
> > Okay, I'll evaluate this internally and see if that can be done.
> > 
> 
> I have checked this, although there is common part between Zonda and Regera
> PLL configure APIs, a different sequence needs to be followed for Zonda, and
> calling this function from zonda_pll_configure would affect the sequence.
> Hence, I think it is better to leave it as is.

Ack.


-- 
With best wishes
Dmitry
Re: [PATCH v2 3/6] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops
Posted by Konrad Dybcio 1 year, 5 months ago 
On 3.07.2024 12:05 PM, Dmitry Baryshkov wrote:
> On Tue, Jul 02, 2024 at 09:20:41PM GMT, Satya Priya Kakitapalli wrote:
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> Regera PLL ops are required to control the Regera PLL from clock
>> controller drivers, thus add support for the same.
> 
> the same what?

I think it bears a similar meaning to "this" in OPP, as in referring to
the main subject in the sentence.. Although I think I've only seen this
phrasing in QC commit messages so far /shrug

Konrad

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