From: Yassine Oudjana <y.oudjana@protonmail.com>
Add DT bindings for for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
.../arm/mediatek/mediatek,infracfg.yaml | 8 +-
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../bindings/clock/mediatek,apmixedsys.yaml | 4 +-
.../bindings/clock/mediatek,topckgen.yaml | 4 +-
MAINTAINERS | 12 +++
.../clock/mediatek,mt6735-apmixedsys.h | 16 ++++
.../clock/mediatek,mt6735-infracfg.h | 25 ++++++
.../clock/mediatek,mt6735-pericfg.h | 37 +++++++++
.../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++
.../reset/mediatek,mt6735-infracfg.h | 31 ++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 ++++++++
11 files changed, 243 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h
create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
index 230b5188a88db..8e3bc240bafd9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -11,9 +11,10 @@ maintainers:
description:
The Mediatek infracfg controller provides various clocks and reset outputs
- to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
- and reset values in <dt-bindings/reset/mt*-reset.h> and
- <dt-bindings/reset/mt*-resets.h>.
+ to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+ and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
+ <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
+ <dt-bindings/reset/mediatek,mt*-infracfg.h>.
properties:
compatible:
@@ -22,6 +23,7 @@ properties:
- enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
+ - mediatek,mt6735-infracfg
- mediatek,mt6765-infracfg
- mediatek,mt6795-infracfg
- mediatek,mt6779-infracfg_ao
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index 33c94c491828e..7fa2dc9bb6b9c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -20,6 +20,7 @@ properties:
- enum:
- mediatek,mt2701-pericfg
- mediatek,mt2712-pericfg
+ - mediatek,mt6735-pericfg
- mediatek,mt6765-pericfg
- mediatek,mt6795-pericfg
- mediatek,mt7622-pericfg
diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
index 685535846cbb7..ba66287fac68b 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
@@ -12,7 +12,8 @@ maintainers:
description:
The Mediatek apmixedsys controller provides PLLs to the system.
- The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>
+ and <dt-bindings/clock/mediatek,mt*-apmixedsys.h>.
properties:
compatible:
@@ -34,6 +35,7 @@ properties:
- enum:
- mediatek,mt2701-apmixedsys
- mediatek,mt2712-apmixedsys
+ - mediatek,mt6735-apmixedsys
- mediatek,mt6765-apmixedsys
- mediatek,mt6779-apmixedsys
- mediatek,mt6795-apmixedsys
diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
index bdf3b55bd56fd..c080fb0a16181 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
@@ -12,7 +12,8 @@ maintainers:
description:
The Mediatek topckgen controller provides various clocks to the system.
- The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h> and
+ <dt-bindings/clock/mediatek,mt*-topckgen.h>.
properties:
compatible:
@@ -31,6 +32,7 @@ properties:
- enum:
- mediatek,mt2701-topckgen
- mediatek,mt2712-topckgen
+ - mediatek,mt6735-topckgen
- mediatek,mt6765-topckgen
- mediatek,mt6779-topckgen
- mediatek,mt6795-topckgen
diff --git a/MAINTAINERS b/MAINTAINERS
index e2d8fdda1737c..8a62cc391eab9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14217,6 +14217,18 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml
F: drivers/mmc/host/mtk-sd.c
+MEDIATEK MT6735 CLOCK & RESET DRIVERS
+M: Yassine Oudjana <y.oudjana@protonmail.com>
+L: linux-clk@vger.kernel.org
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
+F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
+F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
+
MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@nbd.name>
M: Lorenzo Bianconi <lorenzo@kernel.org>
diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
new file mode 100644
index 0000000000000..3dda719fd5d53
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+
+#define ARMPLL 0
+#define MAINPLL 1
+#define UNIVPLL 2
+#define MMPLL 3
+#define MSDCPLL 4
+#define VENCPLL 5
+#define TVDPLL 6
+#define APLL1 7
+#define APLL2 8
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
new file mode 100644
index 0000000000000..a42be76c778d1
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+
+#define CLK_DBG 0
+#define CLK_GCE 1
+#define CLK_TRBG 2
+#define CLK_CPUM 3
+#define CLK_DEVAPC 4
+#define CLK_AUDIO 5
+#define CLK_GCPU 6
+#define CLK_L2C_SRAM 7
+#define CLK_M4U 8
+#define CLK_CLDMA 9
+#define CLK_CONNMCU_BUS 10
+#define CLK_KP 11
+#define CLK_APXGPT 12
+#define CLK_SEJ 13
+#define CLK_CCIF0_AP 14
+#define CLK_CCIF1_AP 15
+#define CLK_PMIC_SPI 16
+#define CLK_PMIC_WRAP 17
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
new file mode 100644
index 0000000000000..72401f009176a
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H
+#define _DT_BINDINGS_CLK_MT6735_PERICFG_H
+
+#define CLK_DISP_PWM 0
+#define CLK_THERM 1
+#define CLK_PWM1 2
+#define CLK_PWM2 3
+#define CLK_PWM3 4
+#define CLK_PWM4 5
+#define CLK_PWM5 6
+#define CLK_PWM6 7
+#define CLK_PWM7 8
+#define CLK_PWM 9
+#define CLK_USB0 10
+#define CLK_IRDA 11
+#define CLK_APDMA 12
+#define CLK_MSDC30_0 13
+#define CLK_MSDC30_1 14
+#define CLK_MSDC30_2 15
+#define CLK_MSDC30_3 16
+#define CLK_UART0 17
+#define CLK_UART1 18
+#define CLK_UART2 19
+#define CLK_UART3 20
+#define CLK_UART4 21
+#define CLK_BTIF 22
+#define CLK_I2C0 23
+#define CLK_I2C1 24
+#define CLK_I2C2 25
+#define CLK_I2C3 26
+#define CLK_AUXADC 27
+#define CLK_SPI0 28
+#define CLK_IRTX 29
+
+#endif
diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
new file mode 100644
index 0000000000000..a771910a4b8a6
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+
+#define AD_SYS_26M_CK 0
+#define CLKPH_MCK_O 1
+#define DMPLL 2
+#define DPI_CK 3
+#define WHPLL_AUDIO_CK 4
+
+#define SYSPLL_D2 5
+#define SYSPLL_D3 6
+#define SYSPLL_D5 7
+#define SYSPLL1_D2 8
+#define SYSPLL1_D4 9
+#define SYSPLL1_D8 10
+#define SYSPLL1_D16 11
+#define SYSPLL2_D2 12
+#define SYSPLL2_D4 13
+#define SYSPLL3_D2 14
+#define SYSPLL3_D4 15
+#define SYSPLL4_D2 16
+#define SYSPLL4_D4 17
+#define UNIVPLL_D2 18
+#define UNIVPLL_D3 19
+#define UNIVPLL_D5 20
+#define UNIVPLL_D26 21
+#define UNIVPLL1_D2 22
+#define UNIVPLL1_D4 23
+#define UNIVPLL1_D8 24
+#define UNIVPLL2_D2 25
+#define UNIVPLL2_D4 26
+#define UNIVPLL2_D8 27
+#define UNIVPLL3_D2 28
+#define UNIVPLL3_D4 29
+#define MSDCPLL_D2 30
+#define MSDCPLL_D4 31
+#define MSDCPLL_D8 32
+#define MSDCPLL_D16 33
+#define VENCPLL_D3 34
+#define TVDPLL_D2 35
+#define TVDPLL_D4 36
+#define DMPLL_D2 37
+#define DMPLL_D4 38
+#define DMPLL_D8 39
+#define AD_SYS_26M_D2 40
+
+#define AXI_SEL 41
+#define MEM_SEL 42
+#define DDRPHY_SEL 43
+#define MM_SEL 44
+#define PWM_SEL 45
+#define VDEC_SEL 46
+#define MFG_SEL 47
+#define CAMTG_SEL 48
+#define UART_SEL 49
+#define SPI_SEL 50
+#define USB20_SEL 51
+#define MSDC50_0_SEL 52
+#define MSDC30_0_SEL 53
+#define MSDC30_1_SEL 54
+#define MSDC30_2_SEL 55
+#define MSDC30_3_SEL 56
+#define AUDIO_SEL 57
+#define AUDINTBUS_SEL 58
+#define PMICSPI_SEL 59
+#define SCP_SEL 60
+#define ATB_SEL 61
+#define DPI0_SEL 62
+#define SCAM_SEL 63
+#define MFG13M_SEL 64
+#define AUD1_SEL 65
+#define AUD2_SEL 66
+#define IRDA_SEL 67
+#define IRTX_SEL 68
+#define DISPPWM_SEL 69
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 0000000000000..5d24c7a1317f8
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+
+#define RST_EMI_REG 0
+#define RST_DRAMC0_AO 1
+#define RST_AP_CIRQ_EINT 3
+#define RST_APXGPT 4
+#define RST_SCPSYS 5
+#define RST_KP 6
+#define RST_PMIC_WRAP 7
+#define RST_CLDMA_AO_TOP 8
+#define RST_EMI 16
+#define RST_CCIF 17
+#define RST_DRAMC0 18
+#define RST_EMI_AO_REG 19
+#define RST_CCIF_AO 20
+#define RST_TRNG 21
+#define RST_SYS_CIRQ 22
+#define RST_GCE 23
+#define RST_M4U 24
+#define RST_CCIF1 25
+#define RST_CLDMA_TOP_PD 26
+#define RST_CBIP_P2P_MFG 27
+#define RST_CBIP_P2P_APMIXED 28
+#define RST_CBIP_P2P_CKSYS 29
+#define RST_CBIP_P2P_MIPI 30
+#define RST_CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 0000000000000..90ee8ed8923fd
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H
+#define _DT_BINDINGS_RESET_MT6735_PERICFG_H
+
+#define RST_UART0 0
+#define RST_UART1 1
+#define RST_UART2 2
+#define RST_UART3 3
+#define RST_UART4 4
+#define RST_BTIF 6
+#define RST_DISP_PWM_PERI 7
+#define RST_PWM 8
+#define RST_AUXADC 10
+#define RST_DMA 11
+#define RST_IRDA 12
+#define RST_IRTX 13
+#define RST_THERM 16
+#define RST_MSDC2 17
+#define RST_MSDC3 17
+#define RST_MSDC0 19
+#define RST_MSDC1 20
+#define RST_I2C0 22
+#define RST_I2C1 23
+#define RST_I2C2 24
+#define RST_I2C3 25
+#define RST_USB 28
+
+#define RST_SPI0 33
+
+#endif
--
2.45.1
Il 26/06/24 22:24, Yassine Oudjana ha scritto: > From: Yassine Oudjana <y.oudjana@protonmail.com> > > Add DT bindings for for the main clock and reset controllers of MT6735 > (apmixedsys, topckgen, infracfg and pericfg). > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> This commit needs just one small nit to be fixed before being ready to be picked, check below... > --- > .../arm/mediatek/mediatek,infracfg.yaml | 8 +- > .../arm/mediatek/mediatek,pericfg.yaml | 1 + > .../bindings/clock/mediatek,apmixedsys.yaml | 4 +- > .../bindings/clock/mediatek,topckgen.yaml | 4 +- > MAINTAINERS | 12 +++ > .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++ > .../clock/mediatek,mt6735-infracfg.h | 25 ++++++ > .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++ > .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++ > .../reset/mediatek,mt6735-infracfg.h | 31 ++++++++ > .../reset/mediatek,mt6735-pericfg.h | 31 ++++++++ > 11 files changed, 243 insertions(+), 5 deletions(-) > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h > create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h > create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h > ..snip.. > diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > new file mode 100644 > index 0000000000000..3dda719fd5d53 > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H > +#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H > + > +#define ARMPLL 0 All of the definitions inside of the clock bindings for MediaTek have a specific format and, for consistency, you *shall* follow that. #define CLK_(ip-name)_(clock) x For example, #define CLK_APMIXED_ARMPLL 0 #define CLK_APMIXED_MAINPLL 1 ... etc > +#define MAINPLL 1 > +#define UNIVPLL 2 > +#define MMPLL 3 > +#define MSDCPLL 4 > +#define VENCPLL 5 > +#define TVDPLL 6 > +#define APLL1 7 > +#define APLL2 8 > + > +#endif > diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h > new file mode 100644 > index 0000000000000..a42be76c778d1 > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H > +#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H > + > +#define CLK_DBG 0 #define CLK_INFRA_DBG 0 #define CLK_INFRA_GCE 1 .....etc > +#define CLK_GCE 1 > +#define CLK_TRBG 2 > +#define CLK_CPUM 3 > +#define CLK_DEVAPC 4 > +#define CLK_AUDIO 5 > +#define CLK_GCPU 6 > +#define CLK_L2C_SRAM 7 > +#define CLK_M4U 8 > +#define CLK_CLDMA 9 > +#define CLK_CONNMCU_BUS 10 > +#define CLK_KP 11 > +#define CLK_APXGPT 12 > +#define CLK_SEJ 13 > +#define CLK_CCIF0_AP 14 > +#define CLK_CCIF1_AP 15 > +#define CLK_PMIC_SPI 16 > +#define CLK_PMIC_WRAP 17 > + > +#endif > diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h > new file mode 100644 > index 0000000000000..72401f009176a > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h > @@ -0,0 +1,37 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H > +#define _DT_BINDINGS_CLK_MT6735_PERICFG_H > + > +#define CLK_DISP_PWM 0 #define CLK_PERI_DISP_PWM #define CLK_PERI_THERM ....etc > +#define CLK_THERM 1 > +#define CLK_PWM1 2 ..snip.. > + > +#endif > diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h > new file mode 100644 > index 0000000000000..a771910a4b8a6 > --- /dev/null > +++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h > @@ -0,0 +1,79 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H > +#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H > + > +#define AD_SYS_26M_CK 0 #define CLK_TOP_AD_SYS_26M_CK #define CLK_TOP_CLKPH_MCK_O #define CLK_TOP_DMPLL ....etc > +#define CLKPH_MCK_O 1 > +#define DMPLL 2 ..snip... > + > +#endif > diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h > new file mode 100644 > index 0000000000000..5d24c7a1317f8 > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h > @@ -0,0 +1,31 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H > +#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H > + For resets, the names are, instead... #define (socmodel)_(ip-name)_(instance)_(reset-name) so, for example... #define MT6735_INFRA_RST0_EMI_REG 0 #define MT6735_INFRA_RST0_DRAMC0_AO 1 and no holes are permitted, so: #define MT6735_INFRA_RST0_AP_CIRQ_EINT 2 ...this means that, unless you know what is at 2, you have to define a .rst_idx_map which will effectively map the binding to the actual real reset bit in the reset register. In the driver: #define RST_NR_PER_BANK 32 static u16 infra_idx_map[] = { [MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0 ...... [MT7635_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3 ... etc }; > +#define RST_EMI_REG 0 > +#define RST_DRAMC0_AO 1 > +#define RST_AP_CIRQ_EINT 3 > +#define RST_APXGPT 4 > +#define RST_SCPSYS 5 > +#define RST_KP 6 > +#define RST_PMIC_WRAP 7 > +#define RST_CLDMA_AO_TOP 8 > +#define RST_EMI 16 > +#define RST_CCIF 17 > +#define RST_DRAMC0 18 > +#define RST_EMI_AO_REG 19 > +#define RST_CCIF_AO 20 > +#define RST_TRNG 21 > +#define RST_SYS_CIRQ 22 > +#define RST_GCE 23 > +#define RST_M4U 24 > +#define RST_CCIF1 25 > +#define RST_CLDMA_TOP_PD 26 > +#define RST_CBIP_P2P_MFG 27 > +#define RST_CBIP_P2P_APMIXED 28 > +#define RST_CBIP_P2P_CKSYS 29 > +#define RST_CBIP_P2P_MIPI 30 > +#define RST_CBIP_P2P_DDRPHY 31 > + > +#endif > diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h > new file mode 100644 > index 0000000000000..90ee8ed8923fd > --- /dev/null > +++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h > @@ -0,0 +1,31 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > + > +#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H > +#define _DT_BINDINGS_RESET_MT6735_PERICFG_H > + > +#define RST_UART0 0 #define MT6735_PERI_RST0_UART0 ......etc You're almost there, getting this stuff upstream is just one small effort ahead. Keep it up! Cheers, Angelo
On Thu, Jun 27, 2024 at 10:37:03AM +0200, AngeloGioacchino Del Regno wrote: > Il 26/06/24 22:24, Yassine Oudjana ha scritto: > > From: Yassine Oudjana <y.oudjana@protonmail.com> > > > > Add DT bindings for for the main clock and reset controllers of MT6735 > > (apmixedsys, topckgen, infracfg and pericfg). > > > > Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> > > This commit needs just one small nit to be fixed before being ready to be picked, > check below... You say "one small nit" and follow it with "you *shall*", dunno if that's really a nit! With the namings fixed up Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor.
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