From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Support "None" alpha blending mode on MediaTek's chips.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 36021cb8df62..48b714994492 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -3,6 +3,7 @@
  * Copyright (c) 2021 MediaTek Inc.
  */
 
+#include <drm/drm_blend.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_framebuffer.h>
 #include <linux/clk.h>
@@ -35,6 +36,7 @@
 #define MIX_SRC_L0_EN				BIT(0)
 #define MIX_L_SRC_CON(n)		(0x28 + 0x18 * (n))
 #define NON_PREMULTI_SOURCE			(2 << 12)
+#define PREMULTI_SOURCE				(3 << 12)
 #define MIX_L_SRC_SIZE(n)		(0x30 + 0x18 * (n))
 #define MIX_L_SRC_OFFSET(n)		(0x34 + 0x18 * (n))
 #define MIX_FUNC_DCM0			0x120
@@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 		alpha_con |= state->base.alpha & MIXER_ALPHA;
 	}
 
-	if (state->base.fb && !state->base.fb->format->has_alpha) {
+	if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
+		alpha_con |= PREMULTI_SOURCE;
+	else
+		alpha_con |= NON_PREMULTI_SOURCE;
+
+	if ((state->base.fb && !state->base.fb->format->has_alpha) ||
+	    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
 		/*
 		 * Mixer doesn't support CONST_BLD mode,
 		 * use a trick to make the output equivalent
@@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 	mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
 		      mixer->regs, MIX_L_SRC_SIZE(idx));
 	mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
-	mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
-			   0x1ff);
+	mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
 			   BIT(idx));
 }

-- 
Git-146)

Hi, Shawn:

On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay wrote:
>  	 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Support "None" alpha blending mode on MediaTek's chips.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 36021cb8df62..48b714994492 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -3,6 +3,7 @@
>   * Copyright (c) 2021 MediaTek Inc.
>   */
>  
> +#include <drm/drm_blend.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_framebuffer.h>
>  #include <linux/clk.h>
> @@ -35,6 +36,7 @@
>  #define MIX_SRC_L0_ENBIT(0)
>  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
>  #define NON_PREMULTI_SOURCE(2 << 12)
> +#define PREMULTI_SOURCE(3 << 12)
>  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
>  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
>  #define MIX_FUNC_DCM00x120
> @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
>  alpha_con |= state->base.alpha & MIXER_ALPHA;
>  }
>  
> -if (state->base.fb && !state->base.fb->format->has_alpha) {
> +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> +alpha_con |= PREMULTI_SOURCE;

To support DRM_MODE_BLEND_PIXEL_NONE, I think ignore pixel alpha is enough. Why need this setting?

Regards,
CK

> +else
> +alpha_con |= NON_PREMULTI_SOURCE;
> +
> +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
>  /*
>   * Mixer doesn't support CONST_BLD mode,
>   * use a trick to make the output equivalent
> @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
>  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
>        mixer->regs, MIX_L_SRC_SIZE(idx));
>  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> -   0x1ff);
> +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
>  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
>     BIT(idx));
>  }
> 
> -- 
> Git-146)
> 
> 
> 

Hi CK,

On Mon, 2024-07-01 at 03:10 +0000, CK Hu (胡俊光) wrote:
> Hi, Shawn:
> 
> On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay
> wrote:
> >  	 
> > External email : Please do not click links or open attachments
> > until you have verified the sender or the content.
> >  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > 
> > Support "None" alpha blending mode on MediaTek's chips.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > index 36021cb8df62..48b714994492 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -3,6 +3,7 @@
> >   * Copyright (c) 2021 MediaTek Inc.
> >   */
> >  
> > +#include <drm/drm_blend.h>
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_framebuffer.h>
> >  #include <linux/clk.h>
> > @@ -35,6 +36,7 @@
> >  #define MIX_SRC_L0_ENBIT(0)
> >  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
> >  #define NON_PREMULTI_SOURCE(2 << 12)
> > +#define PREMULTI_SOURCE(3 << 12)
> >  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
> >  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
> >  #define MIX_FUNC_DCM00x120
> > @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device
> > *dev, unsigned int idx,
> >  alpha_con |= state->base.alpha & MIXER_ALPHA;
> >  }
> >  
> > -if (state->base.fb && !state->base.fb->format->has_alpha) {
> > +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> > +alpha_con |= PREMULTI_SOURCE;
> 
> To support DRM_MODE_BLEND_PIXEL_NONE, I think ignore pixel alpha is
> enough. Why need this setting?

Yes, by setting PREMULTI_SOURCE bit, ETHDR will ignore the pixel alpha
of the layer.

Thanks,
Shawn

> 
> Regards,
> CK
> 
> > +else
> > +alpha_con |= NON_PREMULTI_SOURCE;
> > +
> > +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> > +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
> >  /*
> >   * Mixer doesn't support CONST_BLD mode,
> >   * use a trick to make the output equivalent
> > @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev,
> > unsigned int idx,
> >  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width,
> > &mixer->cmdq_base,
> >        mixer->regs, MIX_L_SRC_SIZE(idx));
> >  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs,
> > MIX_L_SRC_OFFSET(idx));
> > -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_CON(idx),
> > -   0x1ff);
> > +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, 
> > MIX_L_SRC_CON(idx));
> >  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer-
> > >regs, MIX_SRC_CON,
> >     BIT(idx));
> >  }
> > 
> > -- 
> > Git-146)
> > 
> > 
> > 

Hi, Shawn:

On Thu, 2024-07-04 at 01:35 +0000, Shawn Sung (宋孝謙) wrote:
> Hi CK,
> 
> On Mon, 2024-07-01 at 03:10 +0000, CK Hu (胡俊光) wrote:
> > Hi, Shawn:
> > 
> > On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay
> > wrote:
> > >  	 
> > > External email : Please do not click links or open attachments
> > > until you have verified the sender or the content.
> > >  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > 
> > > Support "None" alpha blending mode on MediaTek's chips.
> > > 
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
> > >  1 file changed, 10 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > index 36021cb8df62..48b714994492 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > @@ -3,6 +3,7 @@
> > >   * Copyright (c) 2021 MediaTek Inc.
> > >   */
> > >  
> > > +#include <drm/drm_blend.h>
> > >  #include <drm/drm_fourcc.h>
> > >  #include <drm/drm_framebuffer.h>
> > >  #include <linux/clk.h>
> > > @@ -35,6 +36,7 @@
> > >  #define MIX_SRC_L0_ENBIT(0)
> > >  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
> > >  #define NON_PREMULTI_SOURCE(2 << 12)
> > > +#define PREMULTI_SOURCE(3 << 12)
> > >  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
> > >  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
> > >  #define MIX_FUNC_DCM00x120
> > > @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device
> > > *dev, unsigned int idx,
> > >  alpha_con |= state->base.alpha & MIXER_ALPHA;
> > >  }
> > >  
> > > -if (state->base.fb && !state->base.fb->format->has_alpha) {
> > > +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> > > +alpha_con |= PREMULTI_SOURCE;
> > 
> > To support DRM_MODE_BLEND_PIXEL_NONE, I think ignore pixel alpha is
> > enough. Why need this setting?
> 
> Yes, by setting PREMULTI_SOURCE bit, ETHDR will ignore the pixel alpha
> of the layer.

In the later code, replace_src_a would be set to true.
I think replace_src_a is enough to implement DRM_MODE_BLEND_PIXEL_NONE.
So it's not necessary to set PREMULTI_SOURCE.

Regards,
CK

> 
> Thanks,
> Shawn
> 
> > 
> > Regards,
> > CK
> > 
> > > +else
> > > +alpha_con |= NON_PREMULTI_SOURCE;
> > > +
> > > +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> > > +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
> > >  /*
> > >   * Mixer doesn't support CONST_BLD mode,
> > >   * use a trick to make the output equivalent
> > > @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev,
> > > unsigned int idx,
> > >  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width,
> > > &mixer->cmdq_base,
> > >        mixer->regs, MIX_L_SRC_SIZE(idx));
> > >  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs,
> > > MIX_L_SRC_OFFSET(idx));
> > > -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer-
> > > > regs, MIX_L_SRC_CON(idx),
> > > 
> > > -   0x1ff);
> > > +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, 
> > > MIX_L_SRC_CON(idx));
> > >  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer-
> > > > regs, MIX_SRC_CON,
> > > 
> > >     BIT(idx));
> > >  }
> > > 
> > > -- 
> > > Git-146)
> > > 
> > > 
> > > 

Hi, Shawn:

On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay wrote:
>  	 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Support "None" alpha blending mode on MediaTek's chips.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 36021cb8df62..48b714994492 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -3,6 +3,7 @@
>   * Copyright (c) 2021 MediaTek Inc.
>   */
>  
> +#include <drm/drm_blend.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_framebuffer.h>
>  #include <linux/clk.h>
> @@ -35,6 +36,7 @@
>  #define MIX_SRC_L0_ENBIT(0)
>  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
>  #define NON_PREMULTI_SOURCE(2 << 12)
> +#define PREMULTI_SOURCE(3 << 12)
>  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
>  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
>  #define MIX_FUNC_DCM00x120
> @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
>  alpha_con |= state->base.alpha & MIXER_ALPHA;
>  }
>  
> -if (state->base.fb && !state->base.fb->format->has_alpha) {
> +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> +alpha_con |= PREMULTI_SOURCE;
> +else
> +alpha_con |= NON_PREMULTI_SOURCE;

Coverage mode is an already support mode, but this patch modify alpha_con for coverage mode.
So this is a bug fix?

Regards,
CK

> +
> +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
>  /*
>   * Mixer doesn't support CONST_BLD mode,
>   * use a trick to make the output equivalent
> @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
>  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
>        mixer->regs, MIX_L_SRC_SIZE(idx));
>  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> -   0x1ff);
> +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
>  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
>     BIT(idx));
>  }
> 
> -- 
> Git-146)
> 
> 
> 

Hi CK,

On Mon, 2024-07-01 at 02:22 +0000, CK Hu (胡俊光) wrote:
> Hi, Shawn:
> 
> On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay
> wrote:
> >  	 
> > External email : Please do not click links or open attachments
> > until you have verified the sender or the content.
> >  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > 
> > Support "None" alpha blending mode on MediaTek's chips.
> > 
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > index 36021cb8df62..48b714994492 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -3,6 +3,7 @@
> >   * Copyright (c) 2021 MediaTek Inc.
> >   */
> >  
> > +#include <drm/drm_blend.h>
> >  #include <drm/drm_fourcc.h>
> >  #include <drm/drm_framebuffer.h>
> >  #include <linux/clk.h>
> > @@ -35,6 +36,7 @@
> >  #define MIX_SRC_L0_ENBIT(0)
> >  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
> >  #define NON_PREMULTI_SOURCE(2 << 12)
> > +#define PREMULTI_SOURCE(3 << 12)
> >  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
> >  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
> >  #define MIX_FUNC_DCM00x120
> > @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device
> > *dev, unsigned int idx,
> >  alpha_con |= state->base.alpha & MIXER_ALPHA;
> >  }
> >  
> > -if (state->base.fb && !state->base.fb->format->has_alpha) {
> > +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> > +alpha_con |= PREMULTI_SOURCE;
> > +else
> > +alpha_con |= NON_PREMULTI_SOURCE;
> 
> Coverage mode is an already support mode, but this patch modify
> alpha_con for coverage mode.
> So this is a bug fix?

In oreder to replace the default setting that is set in
mtk_ethdr_config(), we change mtk_ddp_write_mask() to mtk_ddp_write(),
and this change will also reset NON_PREMULTI_SOURCE bit that was
assigned in mtk_ethdr_config(). Therefore, we must still set
NON_PREMULTI_SOURCE bit if the blend mode is not
DRM_MODE_BLEND_PIXEL_NONE.

Regards,
Shawn

> 
> Regards,
> CK
> 
> > +
> > +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> > +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
> >  /*
> >   * Mixer doesn't support CONST_BLD mode,
> >   * use a trick to make the output equivalent
> > @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev,
> > unsigned int idx,
> >  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width,
> > &mixer->cmdq_base,
> >        mixer->regs, MIX_L_SRC_SIZE(idx));
> >  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs,
> > MIX_L_SRC_OFFSET(idx));
> > -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_CON(idx),
> > -   0x1ff);
> > +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, 
> > MIX_L_SRC_CON(idx));
> >  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer-
> > >regs, MIX_SRC_CON,
> >     BIT(idx));
> >  }
> > 
> > -- 
> > Git-146)
> > 
> > 
> > 

Hi, Shawn:

On Thu, 2024-07-04 at 01:43 +0000, Shawn Sung (宋孝謙) wrote:
> Hi CK,
> 
> On Mon, 2024-07-01 at 02:22 +0000, CK Hu (胡俊光) wrote:
> > Hi, Shawn:
> > 
> > On Thu, 2024-06-20 at 01:27 +0800, Hsiao Chien Sung via B4 Relay
> > wrote:
> > >  	 
> > > External email : Please do not click links or open attachments
> > > until you have verified the sender or the content.
> > >  From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > 
> > > Support "None" alpha blending mode on MediaTek's chips.
> > > 
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 ++++++++++---
> > >  1 file changed, 10 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > index 36021cb8df62..48b714994492 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > @@ -3,6 +3,7 @@
> > >   * Copyright (c) 2021 MediaTek Inc.
> > >   */
> > >  
> > > +#include <drm/drm_blend.h>
> > >  #include <drm/drm_fourcc.h>
> > >  #include <drm/drm_framebuffer.h>
> > >  #include <linux/clk.h>
> > > @@ -35,6 +36,7 @@
> > >  #define MIX_SRC_L0_ENBIT(0)
> > >  #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
> > >  #define NON_PREMULTI_SOURCE(2 << 12)
> > > +#define PREMULTI_SOURCE(3 << 12)
> > >  #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
> > >  #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
> > >  #define MIX_FUNC_DCM00x120
> > > @@ -175,7 +177,13 @@ void mtk_ethdr_layer_config(struct device
> > > *dev, unsigned int idx,
> > >  alpha_con |= state->base.alpha & MIXER_ALPHA;
> > >  }
> > >  
> > > -if (state->base.fb && !state->base.fb->format->has_alpha) {
> > > +if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> > > +alpha_con |= PREMULTI_SOURCE;
> > > +else
> > > +alpha_con |= NON_PREMULTI_SOURCE;
> > 
> > Coverage mode is an already support mode, but this patch modify
> > alpha_con for coverage mode.
> > So this is a bug fix?
> 
> In oreder to replace the default setting that is set in
> mtk_ethdr_config(), we change mtk_ddp_write_mask() to mtk_ddp_write(),
> and this change will also reset NON_PREMULTI_SOURCE bit that was
> assigned in mtk_ethdr_config(). Therefore, we must still set
> NON_PREMULTI_SOURCE bit if the blend mode is not
> DRM_MODE_BLEND_PIXEL_NONE.

Add this information in commit message so others would not be confused.

Regards,
CK

> 
> Regards,
> Shawn
> 
> > 
> > Regards,
> > CK
> > 
> > > +
> > > +if ((state->base.fb && !state->base.fb->format->has_alpha) ||
> > > +    state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
> > >  /*
> > >   * Mixer doesn't support CONST_BLD mode,
> > >   * use a trick to make the output equivalent
> > > @@ -191,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev,
> > > unsigned int idx,
> > >  mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width,
> > > &mixer->cmdq_base,
> > >        mixer->regs, MIX_L_SRC_SIZE(idx));
> > >  mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs,
> > > MIX_L_SRC_OFFSET(idx));
> > > -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer-
> > > > regs, MIX_L_SRC_CON(idx),
> > > 
> > > -   0x1ff);
> > > +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, 
> > > MIX_L_SRC_CON(idx));
> > >  mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer-
> > > > regs, MIX_SRC_CON,
> > > 
> > >     BIT(idx));
> > >  }
> > > 
> > > -- 
> > > Git-146)
> > > 
> > > 
> > >