[v5] usb: dwc3: core: Workaround for CSR read timeout

[PATCH v5] usb: dwc3: core: Workaround for CSR read timeout

Posted by joswang 1 year, 7 months ago

From: Jos Wang <joswang@lenovo.com>

This is a workaround for STAR 4846132, which only affects
DWC_usb31 version2.00a operating in host mode.

There is a problem in DWC_usb31 version 2.00a operating
in host mode that would cause a CSR read timeout When CSR
read coincides with RAM Clock Gating Entry. By disable
Clock Gating, sacrificing power consumption for normal
operation.

Cc: stable@vger.kernel.org
Signed-off-by: Jos Wang <joswang@lenovo.com>
---
v4 -> v5: no change
v3 -> v4: modify commit message, add Cc: stable@vger.kernel.org
v2 -> v3:
- code refactor
- modify comment, add STAR number, workaround applied in host mode
- modify commit message, add STAR number, workaround applied in host mode
- modify Author Jos Wang
v1 -> v2: no change

 drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7ee61a89520b..2a3adc80fe0f 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -957,12 +957,16 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
 
 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 {
+	unsigned int power_opt;
+	unsigned int hw_mode;
 	u32 reg;
 
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+	power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
 
-	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
+	switch (power_opt) {
 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 		/**
 		 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
@@ -995,6 +999,20 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 		break;
 	}
 
+	/*
+	 * This is a workaround for STAR#4846132, which only affects
+	 * DWC_usb31 version2.00a operating in host mode.
+	 *
+	 * There is a problem in DWC_usb31 version 2.00a operating
+	 * in host mode that would cause a CSR read timeout When CSR
+	 * read coincides with RAM Clock Gating Entry. By disable
+	 * Clock Gating, sacrificing power consumption for normal
+	 * operation.
+	 */
+	if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
+	    hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
+		reg |= DWC3_GCTL_DSBLCLKGTNG;
+
 	/* check if current dwc3 is on simulation board */
 	if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 		dev_info(dwc->dev, "Running with FPGA optimizations\n");
-- 
2.17.1

Re: [PATCH v5] usb: dwc3: core: Workaround for CSR read timeout

Posted by Thinh Nguyen 1 year, 7 months ago

On Tue, Jun 18, 2024, joswang wrote:
> From: Jos Wang <joswang@lenovo.com>
> 
> This is a workaround for STAR 4846132, which only affects
> DWC_usb31 version2.00a operating in host mode.
> 
> There is a problem in DWC_usb31 version 2.00a operating
> in host mode that would cause a CSR read timeout When CSR
> read coincides with RAM Clock Gating Entry. By disable
> Clock Gating, sacrificing power consumption for normal
> operation.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Jos Wang <joswang@lenovo.com>
> ---
> v4 -> v5: no change
> v3 -> v4: modify commit message, add Cc: stable@vger.kernel.org
> v2 -> v3:
> - code refactor
> - modify comment, add STAR number, workaround applied in host mode
> - modify commit message, add STAR number, workaround applied in host mode
> - modify Author Jos Wang
> v1 -> v2: no change
> 
>  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 7ee61a89520b..2a3adc80fe0f 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -957,12 +957,16 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
>  
>  static void dwc3_core_setup_global_control(struct dwc3 *dwc)
>  {
> +	unsigned int power_opt;
> +	unsigned int hw_mode;
>  	u32 reg;
>  
>  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
>  	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> +	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> +	power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
>  
> -	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> +	switch (power_opt) {
>  	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
>  		/**
>  		 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
> @@ -995,6 +999,20 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
>  		break;
>  	}
>  
> +	/*
> +	 * This is a workaround for STAR#4846132, which only affects
> +	 * DWC_usb31 version2.00a operating in host mode.
> +	 *
> +	 * There is a problem in DWC_usb31 version 2.00a operating
> +	 * in host mode that would cause a CSR read timeout When CSR
> +	 * read coincides with RAM Clock Gating Entry. By disable
> +	 * Clock Gating, sacrificing power consumption for normal
> +	 * operation.
> +	 */
> +	if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
> +	    hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
> +		reg |= DWC3_GCTL_DSBLCLKGTNG;
> +
>  	/* check if current dwc3 is on simulation board */
>  	if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
>  		dev_info(dwc->dev, "Running with FPGA optimizations\n");
> -- 
> 2.17.1
> 

Why are there two v5 patches? This will confuse reviewers. Please create
a new version on every new submission however small the change is.
Please send v6.

Thanks,
Thinh

Re: [PATCH v5] usb: dwc3: core: Workaround for CSR read timeout

Posted by joswang 1 year, 7 months ago

On Wed, Jun 19, 2024 at 5:40 AM Thinh Nguyen <Thinh.Nguyen@synopsys.com> wrote:
>
> On Tue, Jun 18, 2024, joswang wrote:
> > From: Jos Wang <joswang@lenovo.com>
> >
> > This is a workaround for STAR 4846132, which only affects
> > DWC_usb31 version2.00a operating in host mode.
> >
> > There is a problem in DWC_usb31 version 2.00a operating
> > in host mode that would cause a CSR read timeout When CSR
> > read coincides with RAM Clock Gating Entry. By disable
> > Clock Gating, sacrificing power consumption for normal
> > operation.
> >
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Jos Wang <joswang@lenovo.com>
> > ---
> > v4 -> v5: no change
> > v3 -> v4: modify commit message, add Cc: stable@vger.kernel.org
> > v2 -> v3:
> > - code refactor
> > - modify comment, add STAR number, workaround applied in host mode
> > - modify commit message, add STAR number, workaround applied in host mode
> > - modify Author Jos Wang
> > v1 -> v2: no change
> >
> >  drivers/usb/dwc3/core.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 7ee61a89520b..2a3adc80fe0f 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -957,12 +957,16 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
> >
> >  static void dwc3_core_setup_global_control(struct dwc3 *dwc)
> >  {
> > +     unsigned int power_opt;
> > +     unsigned int hw_mode;
> >       u32 reg;
> >
> >       reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> >       reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> > +     hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> > +     power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
> >
> > -     switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> > +     switch (power_opt) {
> >       case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> >               /**
> >                * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
> > @@ -995,6 +999,20 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
> >               break;
> >       }
> >
> > +     /*
> > +      * This is a workaround for STAR#4846132, which only affects
> > +      * DWC_usb31 version2.00a operating in host mode.
> > +      *
> > +      * There is a problem in DWC_usb31 version 2.00a operating
> > +      * in host mode that would cause a CSR read timeout When CSR
> > +      * read coincides with RAM Clock Gating Entry. By disable
> > +      * Clock Gating, sacrificing power consumption for normal
> > +      * operation.
> > +      */
> > +     if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
> > +         hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
> > +             reg |= DWC3_GCTL_DSBLCLKGTNG;
> > +
> >       /* check if current dwc3 is on simulation board */
> >       if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
> >               dev_info(dwc->dev, "Running with FPGA optimizations\n");
> > --
> > 2.17.1
> >
>
> Why are there two v5 patches? This will confuse reviewers. Please create
> a new version on every new submission however small the change is.
> Please send v6.
>
> Thanks,
> Thinh

Sorry, I will submit v6

Thanks，
Jos Wang