On Mon, Jun 17, 2024 at 04:23:07PM GMT, Aradhya Bhatia wrote:
> Allow the DCS Write FIFO in the cdns-dsi controller to reset before any
> DCS packet is transmitted to the DSI sink device.
>
> The DCS FIFO reset is optional. Not all panels require it. But at
> least one of the DSI based panel that uses Ilitek ILI9881C (DSI to DPI
> bridge) doesn't work with without this reset.
Could you please be more specific, why doesn't it work. Are there any
leftover bytes in the FIFO? Is there any additional delay?
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> index 05d2f4cc50da..87fdd07ca0bc 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> @@ -1037,6 +1037,9 @@ static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
>
> cdns_dsi_init_link(dsi);
>
> + /* Reset the DCS Write FIFO */
> + writel(0x00, dsi->regs + DIRECT_CMD_FIFO_RST);
> +
> ret = mipi_dsi_create_packet(&packet, msg);
> if (ret)
> goto out;
> --
> 2.34.1
>
--
With best wishes
Dmitry