arch/riscv/configs/defconfig | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
Add support for StarFive JH7110 SoC and VisionFive 2 board.
- Cache
- Temperature sensor
- PMIC (AXP15060)
- Ethernet PHY (YT8531)
- Restart GPIO
- RNG
- I2C
- SPI
- Quad SPI
- PCIe
- USB & USB 2.0 PHY & PCIe 2.0/USB 3.0 PHY
- Audio (I2S / TDM / PWM-DAC)
- MIPI-CSI2 RX & D-PHY RX
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
As more drivers of StarFive JH7110 VisionFive 2 board are upstream,
add support for them in riscv defconfig.
Changes since v2:
- As the JH7110 PCIe driver was accepted, add CONFIG_PCIE_STARFIVE_HOST=m.
- Add CONFIG_MOTORCOMM_PHY=m, which supports the ethernet phy chips
on the board.
- Rebase on the -next branch.
Changes since v1:
- Drop CONFIG_STAGING=y, CONFIG_STAGING_MEDIA=y,
CONFIG_V4L_PLATFORM_DRIVERS=y, CONFIG_VIDEO_STARFIVE_CAMSS=m.
- Change CONFIG_SENSORS_SFCTEMP as a module.
- Drop CONFIG_CLK_STARFIVE_JH7110_*=y, because they are not critical to boot.
- Update the commit message.
History:
v2: https://lore.kernel.org/all/20240506034627.66765-1-hal.feng@starfivetech.com/
v1: https://lore.kernel.org/all/20240403060902.42834-1-hal.feng@starfivetech.com/
---
arch/riscv/configs/defconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 12dc8c73a8ac..6e10039c5c42 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -110,8 +110,10 @@ CONFIG_PCIEPORTBUS=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCIE_XILINX=y
CONFIG_PCIE_FU740=y
+CONFIG_PCIE_STARFIVE_HOST=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_SIFIVE_CCACHE=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
@@ -143,6 +145,7 @@ CONFIG_RAVB=y
CONFIG_STMMAC_ETH=m
CONFIG_MICREL_PHY=y
CONFIG_MICROSEMI_PHY=y
+CONFIG_MOTORCOMM_PHY=m
CONFIG_CAN_RCAR_CANFD=m
CONFIG_INPUT_MOUSEDEV=y
CONFIG_KEYBOARD_SUN4I_LRADC=m
@@ -155,24 +158,35 @@ CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM_JH7110=m
+CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_MV64XXX=m
CONFIG_I2C_RIIC=y
CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=m
+CONFIG_SPI_PL022=m
CONFIG_SPI_RSPI=m
CONFIG_SPI_SIFIVE=y
CONFIG_SPI_SUN6I=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_GPIO_SIFIVE=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_SENSORS_SFCTEMP=m
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
CONFIG_RZG2L_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_RENESAS_RZG2LWDT=y
+CONFIG_MFD_AXP20X_I2C=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_VIDEO_CADENCE_CSI2RX=m
CONFIG_DRM=m
CONFIG_DRM_RADEON=m
CONFIG_DRM_NOUVEAU=m
@@ -184,6 +198,10 @@ CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_RZ=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_SOC_STARFIVE=m
+CONFIG_SND_SOC_JH7110_PWMDAC=m
+CONFIG_SND_SOC_JH7110_TDM=m
CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SIMPLE_CARD=m
CONFIG_USB=y
@@ -197,6 +215,11 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_RENESAS_USBHS=m
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CDNS3=m
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_STARFIVE=m
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_SUNXI=m
CONFIG_NOP_USB_XCEIV=m
@@ -246,6 +269,9 @@ CONFIG_RZG2L_ADC=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_PHY_SUN4I_USB=m
CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m
+CONFIG_PHY_STARFIVE_JH7110_PCIE=m
+CONFIG_PHY_STARFIVE_JH7110_USB=m
CONFIG_LIBNVDIMM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_EXT4_FS=y
--
2.43.2
From: Conor Dooley <conor.dooley@microchip.com>
On Wed, 05 Jun 2024 15:17:01 +0800, Hal Feng wrote:
> Add support for StarFive JH7110 SoC and VisionFive 2 board.
> - Cache
> - Temperature sensor
> - PMIC (AXP15060)
> - Ethernet PHY (YT8531)
> - Restart GPIO
> - RNG
> - I2C
> - SPI
> - Quad SPI
> - PCIe
> - USB & USB 2.0 PHY & PCIe 2.0/USB 3.0 PHY
> - Audio (I2S / TDM / PWM-DAC)
> - MIPI-CSI2 RX & D-PHY RX
>
> [...]
Applied to riscv-config-for-next, thanks!
[1/1] riscv: defconfig: Enable StarFive JH7110 drivers
https://git.kernel.org/conor/c/d8a7d89abb09
Thanks,
Conor.
On Wed, 05 Jun 2024 00:17:01 PDT (-0700), hal.feng@starfivetech.com wrote: > Add support for StarFive JH7110 SoC and VisionFive 2 board. > - Cache > - Temperature sensor > - PMIC (AXP15060) > - Ethernet PHY (YT8531) > - Restart GPIO > - RNG > - I2C > - SPI > - Quad SPI > - PCIe > - USB & USB 2.0 PHY & PCIe 2.0/USB 3.0 PHY > - Audio (I2S / TDM / PWM-DAC) > - MIPI-CSI2 RX & D-PHY RX > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > > As more drivers of StarFive JH7110 VisionFive 2 board are upstream, > add support for them in riscv defconfig. > > Changes since v2: > - As the JH7110 PCIe driver was accepted, add CONFIG_PCIE_STARFIVE_HOST=m. > - Add CONFIG_MOTORCOMM_PHY=m, which supports the ethernet phy chips > on the board. > - Rebase on the -next branch. > > Changes since v1: > - Drop CONFIG_STAGING=y, CONFIG_STAGING_MEDIA=y, > CONFIG_V4L_PLATFORM_DRIVERS=y, CONFIG_VIDEO_STARFIVE_CAMSS=m. > - Change CONFIG_SENSORS_SFCTEMP as a module. > - Drop CONFIG_CLK_STARFIVE_JH7110_*=y, because they are not critical to boot. > - Update the commit message. > > History: > v2: https://lore.kernel.org/all/20240506034627.66765-1-hal.feng@starfivetech.com/ > v1: https://lore.kernel.org/all/20240403060902.42834-1-hal.feng@starfivetech.com/ > > --- > arch/riscv/configs/defconfig | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 12dc8c73a8ac..6e10039c5c42 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -110,8 +110,10 @@ CONFIG_PCIEPORTBUS=y > CONFIG_PCI_HOST_GENERIC=y > CONFIG_PCIE_XILINX=y > CONFIG_PCIE_FU740=y > +CONFIG_PCIE_STARFIVE_HOST=m > CONFIG_DEVTMPFS=y > CONFIG_DEVTMPFS_MOUNT=y > +CONFIG_SIFIVE_CCACHE=y > CONFIG_MTD=y > CONFIG_MTD_BLOCK=y > CONFIG_MTD_CFI=y > @@ -143,6 +145,7 @@ CONFIG_RAVB=y > CONFIG_STMMAC_ETH=m > CONFIG_MICREL_PHY=y > CONFIG_MICROSEMI_PHY=y > +CONFIG_MOTORCOMM_PHY=m > CONFIG_CAN_RCAR_CANFD=m > CONFIG_INPUT_MOUSEDEV=y > CONFIG_KEYBOARD_SUN4I_LRADC=m > @@ -155,24 +158,35 @@ CONFIG_SERIAL_EARLYCON_RISCV_SBI=y > CONFIG_VIRTIO_CONSOLE=y > CONFIG_HW_RANDOM=y > CONFIG_HW_RANDOM_VIRTIO=y > +CONFIG_HW_RANDOM_JH7110=m > +CONFIG_I2C=y > CONFIG_I2C_CHARDEV=m > +CONFIG_I2C_DESIGNWARE_PLATFORM=y > CONFIG_I2C_MV64XXX=m > CONFIG_I2C_RIIC=y > CONFIG_SPI=y > +CONFIG_SPI_CADENCE_QUADSPI=m > +CONFIG_SPI_PL022=m > CONFIG_SPI_RSPI=m > CONFIG_SPI_SIFIVE=y > CONFIG_SPI_SUN6I=y > # CONFIG_PTP_1588_CLOCK is not set > CONFIG_GPIO_SIFIVE=y > +CONFIG_POWER_RESET_GPIO_RESTART=y > +CONFIG_SENSORS_SFCTEMP=m > CONFIG_CPU_THERMAL=y > CONFIG_DEVFREQ_THERMAL=y > CONFIG_RZG2L_THERMAL=y > CONFIG_WATCHDOG=y > CONFIG_SUNXI_WATCHDOG=y > CONFIG_RENESAS_RZG2LWDT=y > +CONFIG_MFD_AXP20X_I2C=y > CONFIG_REGULATOR=y > CONFIG_REGULATOR_FIXED_VOLTAGE=y > +CONFIG_REGULATOR_AXP20X=y > CONFIG_REGULATOR_GPIO=y > +CONFIG_MEDIA_SUPPORT=m > +CONFIG_VIDEO_CADENCE_CSI2RX=m > CONFIG_DRM=m > CONFIG_DRM_RADEON=m > CONFIG_DRM_NOUVEAU=m > @@ -184,6 +198,10 @@ CONFIG_SOUND=y > CONFIG_SND=y > CONFIG_SND_SOC=y > CONFIG_SND_SOC_RZ=m > +CONFIG_SND_DESIGNWARE_I2S=m > +CONFIG_SND_SOC_STARFIVE=m > +CONFIG_SND_SOC_JH7110_PWMDAC=m > +CONFIG_SND_SOC_JH7110_TDM=m > CONFIG_SND_SOC_WM8978=m > CONFIG_SND_SIMPLE_CARD=m > CONFIG_USB=y > @@ -197,6 +215,11 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y > CONFIG_USB_RENESAS_USBHS=m > CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > +CONFIG_USB_CDNS_SUPPORT=m > +CONFIG_USB_CDNS3=m > +CONFIG_USB_CDNS3_GADGET=y > +CONFIG_USB_CDNS3_HOST=y > +CONFIG_USB_CDNS3_STARFIVE=m > CONFIG_USB_MUSB_HDRC=m > CONFIG_USB_MUSB_SUNXI=m > CONFIG_NOP_USB_XCEIV=m > @@ -246,6 +269,9 @@ CONFIG_RZG2L_ADC=m > CONFIG_RESET_RZG2L_USBPHY_CTRL=y > CONFIG_PHY_SUN4I_USB=m > CONFIG_PHY_RCAR_GEN3_USB2=y > +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m > +CONFIG_PHY_STARFIVE_JH7110_PCIE=m > +CONFIG_PHY_STARFIVE_JH7110_USB=m > CONFIG_LIBNVDIMM=y > CONFIG_NVMEM_SUNXI_SID=y > CONFIG_EXT4_FS=y Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
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