From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add documentation for the pin controller found on the Renesas RZ/V2H(P)
(R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
family:
- Additional bits need to be set during pinmuxing.
- The GPIO pin count is different.
Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
added for the RZ/V2H(P) SoC.
Also, add the 'renesas,output-impedance' property. The drive strength
setting on RZ/V2H(P) depends on the different power rails coming out from
the PMIC (connected via I2C). These power rails (required for drive
strength) can be 1.2V, 1.8V, or 3.3V.
Pins are grouped into 4 groups:
Group 1: Impedance
- 150/75/38/25 ohms (at 3.3V)
- 130/65/33/22 ohms (at 1.8V)
Group 2: Impedance
- 50/40/33/25 ohms (at 1.8V)
Group 3: Impedance
- 150/75/37.5/25 ohms (at 3.3V)
- 130/65/33/22 ohms (at 1.8V)
Group 4: Impedance
- 110/55/30/20 ohms (at 1.8V)
- 150/75/38/25 ohms (at 1.2V)
The 'renesas,output-impedance' property, as documented, can be
[0, 1, 2, 3], these correspond to register bit values that can
be set in the PFC_IOLH_mn register, which adjusts the drive
strength value and is pin-dependent.
As power rail information may not be available very early in the boot
process, the 'renesas,output-impedance' property is added instead of
reusing the 'output-impedance-ohms' property.
Also, allow bias-disable, bias-pull-down and bias-pull-up properties
as these can be used to configure the pins.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- Updated description for renesas,output-impedance property
- Updated commit description
RFC->v2
- Renamed renesas-rzv2h,output-impedance -> renesas,output-impedance
- Updated values for renesas,output-impedance
- Added bias properties
---
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 23 +++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 881e992adca3..957b9f7e7de5 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
- enum:
@@ -66,10 +67,14 @@ properties:
maxItems: 1
resets:
- items:
- - description: GPIO_RSTN signal
- - description: GPIO_PORT_RESETN signal
- - description: GPIO_SPARE_RESETN signal
+ oneOf:
+ - items:
+ - description: GPIO_RSTN signal
+ - description: GPIO_PORT_RESETN signal
+ - description: GPIO_SPARE_RESETN signal
+ - items:
+ - description: PFC main reset
+ - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
additionalProperties:
anyOf:
@@ -111,6 +116,16 @@ additionalProperties:
output-high: true
output-low: true
line-name: true
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ renesas,output-impedance:
+ description: |
+ Output impedance for pins on the RZ/V2H(P) SoC. Values 0, 1, 2, and 3
+ correspond to register bit values that can be set in the PFC_IOLH_mn
+ register, which adjusts the drive strength value and is pin-dependent.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
- type: object
additionalProperties:
--
2.34.1On Thu, May 30, 2024 at 06:38:43PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add documentation for the pin controller found on the Renesas RZ/V2H(P)
> (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
> family:
> - Additional bits need to be set during pinmuxing.
> - The GPIO pin count is different.
>
> Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
> added for the RZ/V2H(P) SoC.
>
> Also, add the 'renesas,output-impedance' property. The drive strength
> setting on RZ/V2H(P) depends on the different power rails coming out from
> the PMIC (connected via I2C). These power rails (required for drive
> strength) can be 1.2V, 1.8V, or 3.3V.
>
> Pins are grouped into 4 groups:
>
> Group 1: Impedance
> - 150/75/38/25 ohms (at 3.3V)
> - 130/65/33/22 ohms (at 1.8V)
>
> Group 2: Impedance
> - 50/40/33/25 ohms (at 1.8V)
>
> Group 3: Impedance
> - 150/75/37.5/25 ohms (at 3.3V)
> - 130/65/33/22 ohms (at 1.8V)
>
> Group 4: Impedance
> - 110/55/30/20 ohms (at 1.8V)
> - 150/75/38/25 ohms (at 1.2V)
>
> The 'renesas,output-impedance' property, as documented, can be
> [0, 1, 2, 3], these correspond to register bit values that can
> be set in the PFC_IOLH_mn register, which adjusts the drive
> strength value and is pin-dependent.
>
> As power rail information may not be available very early in the boot
> process, the 'renesas,output-impedance' property is added instead of
> reusing the 'output-impedance-ohms' property.
>
> Also, allow bias-disable, bias-pull-down and bias-pull-up properties
> as these can be used to configure the pins.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> - Updated description for renesas,output-impedance property
> - Updated commit description
>
> RFC->v2
> - Renamed renesas-rzv2h,output-impedance -> renesas,output-impedance
> - Updated values for renesas,output-impedance
> - Added bias properties
> ---
> .../pinctrl/renesas,rzg2l-pinctrl.yaml | 23 +++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> index 881e992adca3..957b9f7e7de5 100644
> --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> @@ -26,6 +26,7 @@ properties:
> - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
> - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
> - renesas,r9a08g045-pinctrl # RZ/G3S
> + - renesas,r9a09g057-pinctrl # RZ/V2H(P)
>
> - items:
> - enum:
> @@ -66,10 +67,14 @@ properties:
> maxItems: 1
>
> resets:
> - items:
> - - description: GPIO_RSTN signal
> - - description: GPIO_PORT_RESETN signal
> - - description: GPIO_SPARE_RESETN signal
> + oneOf:
> + - items:
> + - description: GPIO_RSTN signal
> + - description: GPIO_PORT_RESETN signal
> + - description: GPIO_SPARE_RESETN signal
> + - items:
> + - description: PFC main reset
> + - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
You need a conditional schema for ensuring the length is 2 for RZ/V2H
and 3 otherwise.
>
> additionalProperties:
> anyOf:
> @@ -111,6 +116,16 @@ additionalProperties:
> output-high: true
> output-low: true
> line-name: true
> + bias-disable: true
> + bias-pull-down: true
> + bias-pull-up: true
> + renesas,output-impedance:
> + description: |
Don't need '|'.
> + Output impedance for pins on the RZ/V2H(P) SoC. Values 0, 1, 2, and 3
Don't repeat values in free form text.
> + correspond to register bit values that can be set in the PFC_IOLH_mn
> + register, which adjusts the drive strength value and is pin-dependent.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
>
> - type: object
> additionalProperties:
> --
> 2.34.1
>
Hi Rob,
Thank you for the review.
On Tue, Jun 4, 2024 at 4:36 PM Rob Herring <robh@kernel.org> wrote:
>
> On Thu, May 30, 2024 at 06:38:43PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add documentation for the pin controller found on the Renesas RZ/V2H(P)
> > (R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
> > family:
> > - Additional bits need to be set during pinmuxing.
> > - The GPIO pin count is different.
> >
> > Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
> > added for the RZ/V2H(P) SoC.
> >
> > Also, add the 'renesas,output-impedance' property. The drive strength
> > setting on RZ/V2H(P) depends on the different power rails coming out from
> > the PMIC (connected via I2C). These power rails (required for drive
> > strength) can be 1.2V, 1.8V, or 3.3V.
> >
> > Pins are grouped into 4 groups:
> >
> > Group 1: Impedance
> > - 150/75/38/25 ohms (at 3.3V)
> > - 130/65/33/22 ohms (at 1.8V)
> >
> > Group 2: Impedance
> > - 50/40/33/25 ohms (at 1.8V)
> >
> > Group 3: Impedance
> > - 150/75/37.5/25 ohms (at 3.3V)
> > - 130/65/33/22 ohms (at 1.8V)
> >
> > Group 4: Impedance
> > - 110/55/30/20 ohms (at 1.8V)
> > - 150/75/38/25 ohms (at 1.2V)
> >
> > The 'renesas,output-impedance' property, as documented, can be
> > [0, 1, 2, 3], these correspond to register bit values that can
> > be set in the PFC_IOLH_mn register, which adjusts the drive
> > strength value and is pin-dependent.
> >
> > As power rail information may not be available very early in the boot
> > process, the 'renesas,output-impedance' property is added instead of
> > reusing the 'output-impedance-ohms' property.
> >
> > Also, allow bias-disable, bias-pull-down and bias-pull-up properties
> > as these can be used to configure the pins.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > - Updated description for renesas,output-impedance property
> > - Updated commit description
> >
> > RFC->v2
> > - Renamed renesas-rzv2h,output-impedance -> renesas,output-impedance
> > - Updated values for renesas,output-impedance
> > - Added bias properties
> > ---
> > .../pinctrl/renesas,rzg2l-pinctrl.yaml | 23 +++++++++++++++----
> > 1 file changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > index 881e992adca3..957b9f7e7de5 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > @@ -26,6 +26,7 @@ properties:
> > - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
> > - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
> > - renesas,r9a08g045-pinctrl # RZ/G3S
> > + - renesas,r9a09g057-pinctrl # RZ/V2H(P)
> >
> > - items:
> > - enum:
> > @@ -66,10 +67,14 @@ properties:
> > maxItems: 1
> >
> > resets:
> > - items:
> > - - description: GPIO_RSTN signal
> > - - description: GPIO_PORT_RESETN signal
> > - - description: GPIO_SPARE_RESETN signal
> > + oneOf:
> > + - items:
> > + - description: GPIO_RSTN signal
> > + - description: GPIO_PORT_RESETN signal
> > + - description: GPIO_SPARE_RESETN signal
> > + - items:
> > + - description: PFC main reset
> > + - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
>
> You need a conditional schema for ensuring the length is 2 for RZ/V2H
> and 3 otherwise.
>
Ok, I will add a conditional schema.
> >
> > additionalProperties:
> > anyOf:
> > @@ -111,6 +116,16 @@ additionalProperties:
> > output-high: true
> > output-low: true
> > line-name: true
> > + bias-disable: true
> > + bias-pull-down: true
> > + bias-pull-up: true
> > + renesas,output-impedance:
> > + description: |
>
> Don't need '|'.
>
Agreed, I will drop it.
> > + Output impedance for pins on the RZ/V2H(P) SoC. Values 0, 1, 2, and 3
>
> Don't repeat values in free form text.
>
OK, I will fix the above and send a v6 series.
Cheers,
Prabhakar
Hi Prabhakar,
On Wed, Jun 5, 2024 at 11:39 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> OK, I will fix the above and send a v6 series.
Please don't drag it out that long ;-)
As the rest of the series looks fine, a v4 should be sufficient.
Actually a v4 of just the first patch would be fine for me, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Thu, Jun 6, 2024 at 8:13 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jun 5, 2024 at 11:39 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > OK, I will fix the above and send a v6 series.
>
> Please don't drag it out that long ;-)
Oops, that was a typo.
> As the rest of the series looks fine, a v4 should be sufficient.
> Actually a v4 of just the first patch would be fine for me, too.
>
As agreed patch 02/15 needs dropping, with that patch 07/14 ("pinctrl:
renesas: pinctrl-rzg2l: Add function pointer for locking/unlocking the
PFC register") does not apply cleanly anymore. Maybe I'll just send v4
for the entire patches?
Cheers,
Prabhakar
Hi Prabhakar,
On Thu, Jun 6, 2024 at 10:38 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Jun 6, 2024 at 8:13 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Jun 5, 2024 at 11:39 AM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > OK, I will fix the above and send a v6 series.
> >
> > Please don't drag it out that long ;-)
> Oops, that was a typo.
>
> > As the rest of the series looks fine, a v4 should be sufficient.
> > Actually a v4 of just the first patch would be fine for me, too.
> >
> As agreed patch 02/15 needs dropping, with that patch 07/14 ("pinctrl:
> renesas: pinctrl-rzg2l: Add function pointer for locking/unlocking the
> PFC register") does not apply cleanly anymore. Maybe I'll just send v4
> for the entire patches?
Fine for me, and up to you.
I can easily drop 02/15, and do a s/BOWI/B0WI/g before applying.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Thu, Jun 6, 2024 at 9:41 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jun 6, 2024 at 10:38 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jun 6, 2024 at 8:13 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Wed, Jun 5, 2024 at 11:39 AM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > OK, I will fix the above and send a v6 series.
> > >
> > > Please don't drag it out that long ;-)
> > Oops, that was a typo.
> >
> > > As the rest of the series looks fine, a v4 should be sufficient.
> > > Actually a v4 of just the first patch would be fine for me, too.
> > >
> > As agreed patch 02/15 needs dropping, with that patch 07/14 ("pinctrl:
> > renesas: pinctrl-rzg2l: Add function pointer for locking/unlocking the
> > PFC register") does not apply cleanly anymore. Maybe I'll just send v4
> > for the entire patches?
>
> Fine for me, and up to you.
> I can easily drop 02/15, and do a s/BOWI/B0WI/g before applying.
>
Thanks, in that case I'll send a v4 for patch #1 only.
Cheers,
Prabhakar
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