New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Acked-by: Andy Shevchenko <andy@kernel.org>
---
 arch/x86/platform/intel-mid/intel-mid.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 7be71c2cdc83..8b8173fb0a43 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -22,6 +22,7 @@
 #include <asm/mpspec_def.h>
 #include <asm/hw_irq.h>
 #include <asm/apic.h>
+#include <asm/cpu_device_id.h>
 #include <asm/io_apic.h>
 #include <asm/intel-mid.h>
 #include <asm/io.h>
@@ -55,9 +56,9 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-	switch (boot_cpu_data.x86_model) {
-	case 0x3C:
-	case 0x4A:
+	switch (boot_cpu_data.x86_vfm) {
+	case INTEL_HASWELL:
+	case INTEL_ATOM_SILVERMONT_MID:
 		x86_platform.legacy.rtc = 1;
 		break;
 	default:
-- 
2.45.0

On Mon, May 20, 2024 at 03:45:47PM -0700, Tony Luck wrote:
> New CPU #defines encode vendor and family as well as model.

...

> -	switch (boot_cpu_data.x86_model) {
> -	case 0x3C:
> -	case 0x4A:
> +	switch (boot_cpu_data.x86_vfm) {
> +	case INTEL_HASWELL:

Thanks, God^W your series, I just realised that this is quite a mistake.
I mean, you need to remove this line (with HASWELL) from this file.

  Fixes: bc20aa48bbb3 ("x86, intel-mid: Add Merrifield platform support")

HASWELL was never a part of Intel MID initiative (in a sense how it's
organised in HW and FW).

> +	case INTEL_ATOM_SILVERMONT_MID:
>  		x86_platform.legacy.rtc = 1;
>  		break;

So, TL;DR: Please add the patch, I will give a tag to it immediately.

-- 
With Best Regards,
Andy Shevchenko

New CPU #defines encode vendor and family as well as model.

N.B. Drop Haswell. CPU model 0x3C was included by mistake
in upstream code.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Acked-by: Andy Shevchenko <andy@kernel.org>
---
 arch/x86/platform/intel-mid/intel-mid.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 7be71c2cdc83..f83bbe0acd4a 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -22,6 +22,7 @@
 #include <asm/mpspec_def.h>
 #include <asm/hw_irq.h>
 #include <asm/apic.h>
+#include <asm/cpu_device_id.h>
 #include <asm/io_apic.h>
 #include <asm/intel-mid.h>
 #include <asm/io.h>
@@ -55,9 +56,8 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-	switch (boot_cpu_data.x86_model) {
-	case 0x3C:
-	case 0x4A:
+	switch (boot_cpu_data.x86_vfm) {
+	case INTEL_ATOM_SILVERMONT_MID:
 		x86_platform.legacy.rtc = 1;
 		break;
 	default:
-- 
2.45.0

On Tue, May 21, 2024 at 09:10:01AM -0700, Tony Luck wrote:
> New CPU #defines encode vendor and family as well as model.
> 
> N.B. Drop Haswell. CPU model 0x3C was included by mistake
> in upstream code.

Yep, the result looks good. Dunno if it's better to have a separate patch with
proper Fixes tag. Up to you, folks.

-- 
With Best Regards,
Andy Shevchenko