Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
1 cluster/4 VPU configurations.

v4:
 - Re-base onto the master branch, with no functionality impact.
 - Refactor MIPS FDC driver in the context of multicluster support.

v3:
 - Add Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> for the patch 02/12.
 - Add the changes requested by Marc Zyngier for the 3/12 patch.
 - Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang
   and Marc Zyngier.
 - Re-base onto the master branch, with no functionality impact.

v2:
 - Apply correct Signed-off-by to avoid confusion.

Aleksandar Rikalo (3):
  mips: Enable FDC on MIPS R6 platforms.
  mips: Move FDC driver to a separate directory
  mips: FDC driver refactor

Chao-ying Fu (1):
  irqchip: mips-gic: Setup defaults in each cluster

Paul Burton (10):
  MIPS: CPS: Add a couple of multi-cluster utility functions
  MIPS: GIC: Generate redirect block accessors
  irqchip: mips-gic: Introduce for_each_online_cpu_gic()
  irqchip: mips-gic: Support multi-cluster in for_each_online_cpu_gic()
  irqchip: mips-gic: Multi-cluster support
  clocksource: mips-gic-timer: Always use cluster 0 counter as
    clocksource
  clocksource: mips-gic-timer: Enable counter when CPUs start
  MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core
  MIPS: CPS: Introduce struct cluster_boot_config
  MIPS: CPS: Boot CPUs in secondary clusters

 arch/mips/include/asm/mips-cm.h               |  18 ++
 arch/mips/include/asm/mips-cps.h              |  38 +++
 arch/mips/include/asm/mips-gic.h              |  50 ++-
 arch/mips/include/asm/smp-cps.h               |   7 +-
 arch/mips/kernel/asm-offsets.c                |   3 +
 arch/mips/kernel/cps-vec.S                    |  19 +-
 arch/mips/kernel/mips-cm.c                    |  41 ++-
 arch/mips/kernel/pm-cps.c                     |  35 ++-
 arch/mips/kernel/smp-cps.c                    | 288 ++++++++++++++----
 drivers/bus/Kconfig                           |   2 +-
 drivers/clocksource/mips-gic-timer.c          |  45 ++-
 drivers/irqchip/Kconfig                       |   1 +
 drivers/irqchip/irq-mips-gic.c                | 276 ++++++++++++++---
 drivers/tty/Makefile                          |   2 +-
 drivers/tty/mips_fdc/Makefile                 |   4 +
 drivers/tty/mips_fdc/ejtag-fdc-mips.c         |  29 ++
 .../ejtag-fdc.c}                              |  66 +---
 drivers/tty/mips_fdc/ejtag-fdc.h              |  55 ++++
 18 files changed, 794 insertions(+), 185 deletions(-)
 create mode 100644 drivers/tty/mips_fdc/Makefile
 create mode 100644 drivers/tty/mips_fdc/ejtag-fdc-mips.c
 rename drivers/tty/{mips_ejtag_fdc.c => mips_fdc/ejtag-fdc.c} (92%)
 create mode 100644 drivers/tty/mips_fdc/ejtag-fdc.h

-- 
2.25.1

Hi folks,

On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
> 1 cluster/4 VPU configurations.

Finally got it tested on my P5600-based SoC. No problems has been
spotted. So for the entire patchset:

Tested-by: Serge Semin <fancer.lancer@gmail.com>

> 
> v4:
>  - Re-base onto the master branch, with no functionality impact.


>  - Refactor MIPS FDC driver in the context of multicluster support.

I failed to see anything useful in the MIPS FDC refactoring. Besides
there is no patches utilizing the change provided in the patches 13
and 14 with the refactoring. The commits log don't well justify the
changes either. Moreover the commit log of the patch providing the
actual refactoring says "Separate the FDC driver code into two parts,
common and mips-specific." Has _MIPS_ FDC been utilized in some
non-MIPS arch, or what?

To sum up I'd drop the FDC refactoring patches from these series and
have them added to the patchset where the changes are actually needed
(if there is one).

-Serge(y)

> 
> v3:
>  - Add Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> for the patch 02/12.
>  - Add the changes requested by Marc Zyngier for the 3/12 patch.
>  - Remove the patch 11/12 (a consequence of a discussion between Jiaxun Yang
>    and Marc Zyngier.
>  - Re-base onto the master branch, with no functionality impact.
> 
> v2:
>  - Apply correct Signed-off-by to avoid confusion.
> 
> Aleksandar Rikalo (3):
>   mips: Enable FDC on MIPS R6 platforms.
>   mips: Move FDC driver to a separate directory
>   mips: FDC driver refactor
> 
> Chao-ying Fu (1):
>   irqchip: mips-gic: Setup defaults in each cluster
> 
> Paul Burton (10):
>   MIPS: CPS: Add a couple of multi-cluster utility functions
>   MIPS: GIC: Generate redirect block accessors
>   irqchip: mips-gic: Introduce for_each_online_cpu_gic()
>   irqchip: mips-gic: Support multi-cluster in for_each_online_cpu_gic()
>   irqchip: mips-gic: Multi-cluster support
>   clocksource: mips-gic-timer: Always use cluster 0 counter as
>     clocksource
>   clocksource: mips-gic-timer: Enable counter when CPUs start
>   MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core
>   MIPS: CPS: Introduce struct cluster_boot_config
>   MIPS: CPS: Boot CPUs in secondary clusters
> 
>  arch/mips/include/asm/mips-cm.h               |  18 ++
>  arch/mips/include/asm/mips-cps.h              |  38 +++
>  arch/mips/include/asm/mips-gic.h              |  50 ++-
>  arch/mips/include/asm/smp-cps.h               |   7 +-
>  arch/mips/kernel/asm-offsets.c                |   3 +
>  arch/mips/kernel/cps-vec.S                    |  19 +-
>  arch/mips/kernel/mips-cm.c                    |  41 ++-
>  arch/mips/kernel/pm-cps.c                     |  35 ++-
>  arch/mips/kernel/smp-cps.c                    | 288 ++++++++++++++----
>  drivers/bus/Kconfig                           |   2 +-
>  drivers/clocksource/mips-gic-timer.c          |  45 ++-
>  drivers/irqchip/Kconfig                       |   1 +
>  drivers/irqchip/irq-mips-gic.c                | 276 ++++++++++++++---
>  drivers/tty/Makefile                          |   2 +-
>  drivers/tty/mips_fdc/Makefile                 |   4 +
>  drivers/tty/mips_fdc/ejtag-fdc-mips.c         |  29 ++
>  .../ejtag-fdc.c}                              |  66 +---
>  drivers/tty/mips_fdc/ejtag-fdc.h              |  55 ++++
>  18 files changed, 794 insertions(+), 185 deletions(-)
>  create mode 100644 drivers/tty/mips_fdc/Makefile
>  create mode 100644 drivers/tty/mips_fdc/ejtag-fdc-mips.c
>  rename drivers/tty/{mips_ejtag_fdc.c => mips_fdc/ejtag-fdc.c} (92%)
>  create mode 100644 drivers/tty/mips_fdc/ejtag-fdc.h
> 
> -- 
> 2.25.1
>

Hello everyone,

Thank you for the review and testing!

I will send a new version of the series soon. I will dump the FDC
changes (patches 12, 13, and 14) and include the requested changes.

-- Aleksandar

On Mon, Jun 24, 2024 at 10:12 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> Finally got it tested on my P5600-based SoC. No problems has been
> spotted. So for the entire patchset:
>
> Tested-by: Serge Semin <fancer.lancer@gmail.com>
>
> To sum up I'd drop the FDC refactoring patches from these series and
> have them added to the patchset where the changes are actually needed
> (if there is one).
>

On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
> 1 cluster/4 VPU configurations.

which existing CPUs can use this ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

在2024年6月20日六月 下午6:56，Thomas Bogendoerfer写道：
> On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
>> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
>> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
>> 1 cluster/4 VPU configurations.
>
> which existing CPUs can use this ?

Besides Boston are some multi cluster I6500 systems in wild, including Fungible F1,
which comes with 52 cores in data panel.

Those vendors show no interest on mainline kernel support though.

>
> Thomas.
>
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

-- 
- Jiaxun

On Fri, Jun 21, 2024 at 12:05:32AM +0100, Jiaxun Yang wrote:
> 
> 
> 在2024年6月20日六月 下午6:56，Thomas Bogendoerfer写道：
> > On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
> >> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
> >> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
> >> 1 cluster/4 VPU configurations.
> >
> > which existing CPUs can use this ?
> 
> Besides Boston are some multi cluster I6500 systems in wild, including Fungible F1,
> which comes with 52 cores in data panel.
> 
> Those vendors show no interest on mainline kernel support though.

ok, so looking at the series it touches areas with different maintainers,
I'm fine taking the MIPS parts, can I simply cherry-pick them out
of the series ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

在2024年6月21日六月 上午9:21，Thomas Bogendoerfer写道：
> On Fri, Jun 21, 2024 at 12:05:32AM +0100, Jiaxun Yang wrote:
>> 
>> 
>> 在2024年6月20日六月 下午6:56，Thomas Bogendoerfer写道：
>> > On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
>> >> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
>> >> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
>> >> 1 cluster/4 VPU configurations.
>> >
>> > which existing CPUs can use this ?
>> 
>> Besides Boston are some multi cluster I6500 systems in wild, including Fungible F1,
>> which comes with 52 cores in data panel.
>> 
>> Those vendors show no interest on mainline kernel support though.
>
> ok, so looking at the series it touches areas with different maintainers,
> I'm fine taking the MIPS parts, can I simply cherry-pick them out
> of the series ?

For irqchip part I think it must be taken together with MIPS arch part.
It's a part of MIPS CORE DRIVERS maintainers entry as well.

For FDC I think functionally it's not a prerequisite.

Thanks
>
> Thomas.
>
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

-- 
- Jiaxun

Hi Thomas, Jiaxun

On Fri, Jun 21, 2024 at 10:21:17AM +0200, Thomas Bogendoerfer wrote:
> On Fri, Jun 21, 2024 at 12:05:32AM +0100, Jiaxun Yang wrote:
> > 
> > 
> > 在2024年6月20日六月 下午6:56，Thomas Bogendoerfer写道：
> > > On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
> > >> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
> > >> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
> > >> 1 cluster/4 VPU configurations.
> > >
> > > which existing CPUs can use this ?
> > 
> > Besides Boston are some multi cluster I6500 systems in wild, including Fungible F1,
> > which comes with 52 cores in data panel.
> > 
> > Those vendors show no interest on mainline kernel support though.
> 

> ok, so looking at the series it touches areas with different maintainers,
> I'm fine taking the MIPS parts, can I simply cherry-pick them out
> of the series ?

Please hold on with merging it in for a bit. I'll give the series a
try on my MIPS P5600-based SoC later, on this weekends.

-Serge(y)

> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]

Hi folks,

On Fri, Jun 21, 2024 at 12:13:29PM +0300, Serge Semin wrote:
> Hi Thomas, Jiaxun
> 
> On Fri, Jun 21, 2024 at 10:21:17AM +0200, Thomas Bogendoerfer wrote:
> > On Fri, Jun 21, 2024 at 12:05:32AM +0100, Jiaxun Yang wrote:
> > > 
> > > 
> > > 在2024年6月20日六月 下午6:56，Thomas Bogendoerfer写道：
> > > > On Sat, May 11, 2024 at 12:43:27PM +0200, Aleksandar Rikalo wrote:
> > > >> Taken from Paul Burton MIPS repo with minor changes from Chao-ying Fu.
> > > >> Tested with 64r6el_defconfig on Boston board in 2 cluster/2 VPU and
> > > >> 1 cluster/4 VPU configurations.
> > > >
> > > > which existing CPUs can use this ?
> > > 
> > > Besides Boston are some multi cluster I6500 systems in wild, including Fungible F1,
> > > which comes with 52 cores in data panel.
> > > 
> > > Those vendors show no interest on mainline kernel support though.
> > 
> 
> > ok, so looking at the series it touches areas with different maintainers,
> > I'm fine taking the MIPS parts, can I simply cherry-pick them out
> > of the series ?
> 
> Please hold on with merging it in for a bit. I'll give the series a
> try on my MIPS P5600-based SoC later, on this weekends.

I haven't been able to reach my HW treasury on this weekend. But today
(on Monday) I'll definitely do that and test out the series. Sorry for
the delay.

-Serge(y)

> 
> -Serge(y)
> 
> > 
> > Thomas.
> > 
> > -- 
> > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> > good idea.                                                [ RFC1925, 2.3 ]