Following the failure observed with a delay of 250us, experiments were
conducted with various delays. It was found that a delay of 350us
effectively mitigated the issue.

To provide a more optimal solution while still allowing a margin for
stability, the delay is being adjusted to 500us.

Signed-off-by: Lakshmi Yadlapati <lakshmiy@us.ibm.com>
---
 drivers/hwmon/pmbus/ucd9000.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/hwmon/pmbus/ucd9000.c b/drivers/hwmon/pmbus/ucd9000.c
index 8d9d422450e5..d817c719b90b 100644
--- a/drivers/hwmon/pmbus/ucd9000.c
+++ b/drivers/hwmon/pmbus/ucd9000.c
@@ -80,11 +80,11 @@ struct ucd9000_debugfs_entry {
  * It has been observed that the UCD90320 randomly fails register access when
  * doing another access right on the back of a register write. To mitigate this
  * make sure that there is a minimum delay between a write access and the
- * following access. The 250us is based on experimental data. At a delay of
- * 200us the issue seems to go away. Add a bit of extra margin to allow for
+ * following access. The 500 is based on experimental data. At a delay of
+ * 350us the issue seems to go away. Add a bit of extra margin to allow for
  * system to system differences.
  */
-#define UCD90320_WAIT_DELAY_US 250
+#define UCD90320_WAIT_DELAY_US 500
 
 static inline void ucd90320_wait(const struct ucd9000_data *data)
 {
-- 
2.40.1

On Tue, May 07, 2024 at 02:46:03PM -0500, Lakshmi Yadlapati wrote:
> Following the failure observed with a delay of 250us, experiments were
> conducted with various delays. It was found that a delay of 350us
> effectively mitigated the issue.
> 
> To provide a more optimal solution while still allowing a margin for
> stability, the delay is being adjusted to 500us.
> 
> Signed-off-by: Lakshmi Yadlapati <lakshmiy@us.ibm.com>

Why did you not send this patch to the hardware monitoring mailing list ?
Such an omission all but guarantees that it gets lost, so you should not
be surprised if that happens with your patches if you do that on a regular
basis.

I am going to apply your patch (fortunately I still had it in my inbox),
but please keep that in mind for the future if you want your patches
applied.

Thanks,
Guenter

> ---
>  drivers/hwmon/pmbus/ucd9000.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hwmon/pmbus/ucd9000.c b/drivers/hwmon/pmbus/ucd9000.c
> index 8d9d422450e5..d817c719b90b 100644
> --- a/drivers/hwmon/pmbus/ucd9000.c
> +++ b/drivers/hwmon/pmbus/ucd9000.c
> @@ -80,11 +80,11 @@ struct ucd9000_debugfs_entry {
>   * It has been observed that the UCD90320 randomly fails register access when
>   * doing another access right on the back of a register write. To mitigate this
>   * make sure that there is a minimum delay between a write access and the
> - * following access. The 250us is based on experimental data. At a delay of
> - * 200us the issue seems to go away. Add a bit of extra margin to allow for
> + * following access. The 500 is based on experimental data. At a delay of
> + * 350us the issue seems to go away. Add a bit of extra margin to allow for
>   * system to system differences.
>   */
> -#define UCD90320_WAIT_DELAY_US 250
> +#define UCD90320_WAIT_DELAY_US 500
>  
>  static inline void ucd90320_wait(const struct ucd9000_data *data)
>  {
> -- 
> 2.40.1
>

On 5/7/24 14:46, Lakshmi Yadlapati wrote:
> Following the failure observed with a delay of 250us, experiments were
> conducted with various delays. It was found that a delay of 350us
> effectively mitigated the issue.
>
> To provide a more optimal solution while still allowing a margin for
> stability, the delay is being adjusted to 500us.


Reviewed-by: Eddie James <eajames@linux.ibm.com>


>
> Signed-off-by: Lakshmi Yadlapati <lakshmiy@us.ibm.com>
> ---
>   drivers/hwmon/pmbus/ucd9000.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/hwmon/pmbus/ucd9000.c b/drivers/hwmon/pmbus/ucd9000.c
> index 8d9d422450e5..d817c719b90b 100644
> --- a/drivers/hwmon/pmbus/ucd9000.c
> +++ b/drivers/hwmon/pmbus/ucd9000.c
> @@ -80,11 +80,11 @@ struct ucd9000_debugfs_entry {
>    * It has been observed that the UCD90320 randomly fails register access when
>    * doing another access right on the back of a register write. To mitigate this
>    * make sure that there is a minimum delay between a write access and the
> - * following access. The 250us is based on experimental data. At a delay of
> - * 200us the issue seems to go away. Add a bit of extra margin to allow for
> + * following access. The 500 is based on experimental data. At a delay of
> + * 350us the issue seems to go away. Add a bit of extra margin to allow for
>    * system to system differences.
>    */
> -#define UCD90320_WAIT_DELAY_US 250
> +#define UCD90320_WAIT_DELAY_US 500
>   
>   static inline void ucd90320_wait(const struct ucd9000_data *data)
>   {