1. Patchew
  2. linux
  3. View series

[PATCH] dt-bindings: pci: altera: covert to yaml

matthew.gerlach@linux.intel.com posted 1 patch 1 year, 10 months ago 
.../devicetree/bindings/pci/altera-pcie.txt   |  50 ---------
.../bindings/pci/altr,pcie-root-port.yaml     | 106 ++++++++++++++++++
2 files changed, 106 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
[PATCH] dt-bindings: pci: altera: covert to yaml
Posted by matthew.gerlach@linux.intel.com 1 year, 10 months ago 
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Covert the device tree bindings for the Altera Root
Port controller from text to yaml.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 .../devicetree/bindings/pci/altera-pcie.txt   |  50 ---------
 .../bindings/pci/altr,pcie-root-port.yaml     | 106 ++++++++++++++++++
 2 files changed, 106 insertions(+), 50 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
deleted file mode 100644
index 816b244a221e..000000000000
--- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Altera PCIe controller
-
-Required properties:
-- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
-- reg:		a list of physical base address and length for TXS and CRA.
-		For "altr,pcie-root-port-2.0", additional HIP base address and length.
-- reg-names:	must include the following entries:
-		"Txs": TX slave port region
-		"Cra": Control register access region
-		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
-- interrupts:	specifies the interrupt source of the parent interrupt
-		controller.  The format of the interrupt specifier depends
-		on the parent interrupt controller.
-- device_type:	must be "pci"
-- #address-cells:	set to <3>
-- #size-cells:		set to <2>
-- #interrupt-cells:	set to <1>
-- ranges:	describes the translation of addresses for root ports and
-		standard PCI regions.
-- interrupt-map-mask and interrupt-map: standard PCI properties to define the
-		mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- msi-parent:	Link to the hardware entity that serves as the MSI controller
-		for this PCIe controller.
-- bus-range:	PCI bus numbers covered
-
-Example
-	pcie_0: pcie@c00000000 {
-		compatible = "altr,pcie-root-port-1.0";
-		reg = <0xc0000000 0x20000000>,
-			<0xff220000 0x00004000>;
-		reg-names = "Txs", "Cra";
-		interrupt-parent = <&hps_0_arm_gic_0>;
-		interrupts = <0 40 4>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		bus-range = <0x0 0xFF>;
-		device_type = "pci";
-		msi-parent = <&msi_to_gic_gen_0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_0 1>,
-			            <0 0 0 2 &pcie_0 2>,
-			            <0 0 0 3 &pcie_0 3>,
-			            <0 0 0 4 &pcie_0 4>;
-		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
-			  0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
-	};
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
new file mode 100644
index 000000000000..8f1ad1362ad1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2024, Intel Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera PCIe Root Port
+
+maintainers:
+  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - altr,pcie-root-port-1.0
+          - altr,pcie-root-port-2.0
+
+  reg:
+    minItems: 2
+    maxItems: 3
+
+  reg-names:
+    description:
+      TX slave port region (Txs)
+      Control register access region (Cra)
+      Hard IP region if altr,pcie-root-port-2.0 (Hip)
+
+    items:
+      - const: Txs
+      - const: Cra
+      - const: Hip
+    minItems: 2
+
+  device_type:
+    const: pci
+
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2
+
+  interrupts:
+    minItems: 1
+
+  interrupt-map-mask:
+    items:
+      - const: 0
+      - const: 0
+      - const: 0
+      - const: 7
+
+  interrupt-map:
+    maxItems: 4
+
+  "#interrupt-cells":
+    const: 1
+
+  msi-parent:
+    description: Link to the hardware entity that serves as the MSI controller.
+
+  bus-range:
+    description: PCI bus numbers covered.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - device_type
+  - "#address-cells"
+  - "#size-cells"
+  - interrupts
+  - interrupt-map
+  - interrupt-map-mask
+  - "#interrupt-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pcie_0: pcie@c00000000 {
+        compatible = "altr,pcie-root-port-1.0";
+        reg = <0xc0000000 0x20000000>,
+            <0xff220000 0x00004000>;
+        reg-names = "Txs", "Cra";
+        interrupt-parent = <&hps_0_arm_gic_0>;
+        interrupts = <0 40 4>;
+        #interrupt-cells = <1>;
+        bus-range = <0x0 0xFF>;
+        device_type = "pci";
+        msi-parent = <&msi_to_gic_gen_0>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0 0 0 1 &pcie_intc 1>,
+                        <0 0 0 2 &pcie_intc 2>,
+                        <0 0 0 3 &pcie_intc 3>,
+                        <0 0 0 4 &pcie_intc 4>;
+        ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
+              0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
+    };
-- 
2.34.1
Re: [PATCH] dt-bindings: pci: altera: covert to yaml
Posted by Bjorn Helgaas 1 year, 10 months ago 
"git log --oneline Documentation/devicetree/bindings/pci/" says the
typical style would be:

  dt-bindings: PCI: altera: Convert to YAML

On Fri, Mar 29, 2024 at 12:00:31PM -0500, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Covert the device tree bindings for the Altera Root
> Port controller from text to yaml.

s/covert/convert/ (both in subject and commit log).

Rewrap to fill 80 columns.
Re: [PATCH] dt-bindings: pci: altera: covert to yaml
Posted by matthew.gerlach@linux.intel.com 1 year, 10 months ago 

On Mon, 1 Apr 2024, Bjorn Helgaas wrote:

> "git log --oneline Documentation/devicetree/bindings/pci/" says the
> typical style would be:
>
>  dt-bindings: PCI: altera: Convert to YAML

Good suggestion about the 'git log --oneline ...' I will update title in 
v2.

>
> On Fri, Mar 29, 2024 at 12:00:31PM -0500, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Covert the device tree bindings for the Altera Root
>> Port controller from text to yaml.
>
> s/covert/convert/ (both in subject and commit log).
>
> Rewrap to fill 80 columns.
>

Thanks for catching the spelling error. Wrapping and spelling fix will be 
included in v2.

Matthew Gerlach
Re: [PATCH] dt-bindings: pci: altera: covert to yaml
Posted by Krzysztof Kozlowski 1 year, 10 months ago 
On 29/03/2024 18:00, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Covert the device tree bindings for the Altera Root
> Port controller from text to yaml.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---

...

> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> new file mode 100644
> index 000000000000..8f1ad1362ad1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> @@ -0,0 +1,106 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2024, Intel Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera PCIe Root Port
> +
> +maintainers:
> +  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - altr,pcie-root-port-1.0
> +          - altr,pcie-root-port-2.0
> +
> +  reg:
> +    minItems: 2
> +    maxItems: 3
> +
> +  reg-names:
> +    description:
> +      TX slave port region (Txs)
> +      Control register access region (Cra)
> +      Hard IP region if altr,pcie-root-port-2.0 (Hip)

All these go to reg as description of items.

Both - reg and reg-names - need constraints per variant in
allOf:if:then:. Move allOf: to bottom of file, just like example-schema
is showing.


> + 
> +    items:
> +      - const: Txs
> +      - const: Cra
> +      - const: Hip
> +    minItems: 2
> +
> +  device_type:
> +    const: pci

I don't think you need it.

> +
> +  "#address-cells":
> +    const: 3

Drop

> +
> +  "#size-cells":
> +    const: 2

Drop

> +
> +  interrupts:
> +    minItems: 1

This should be maxItems.

> +
> +  interrupt-map-mask:
> +    items:
> +      - const: 0
> +      - const: 0
> +      - const: 0
> +      - const: 7

I guess as well.

> +
> +  interrupt-map:
> +    maxItems: 4
> +
> +  "#interrupt-cells":
> +    const: 1

Drop

> +
> +  msi-parent:
> +    description: Link to the hardware entity that serves as the MSI controller.

Just true.

Please open existing, recent PCI bindings and look how it is done.

> +
> +  bus-range:
> +    description: PCI bus numbers covered.

Drop

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - device_type
> +  - "#address-cells"
> +  - "#size-cells"
> +  - interrupts
> +  - interrupt-map
> +  - interrupt-map-mask
> +  - "#interrupt-cells"

This also needs cleaning.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    pcie_0: pcie@c00000000 {
> +        compatible = "altr,pcie-root-port-1.0";
> +        reg = <0xc0000000 0x20000000>,
> +            <0xff220000 0x00004000>;

Misaligned.

> +        reg-names = "Txs", "Cra";
> +        interrupt-parent = <&hps_0_arm_gic_0>;
> +        interrupts = <0 40 4>;

Use defines for common constnats.

> +        #interrupt-cells = <1>;
> +        bus-range = <0x0 0xFF>;

Lowercase hex

> +        device_type = "pci";
> +        msi-parent = <&msi_to_gic_gen_0>;
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        interrupt-map-mask = <0 0 0 7>;
> +        interrupt-map = <0 0 0 1 &pcie_intc 1>,
> +                        <0 0 0 2 &pcie_intc 2>,
> +                        <0 0 0 3 &pcie_intc 3>,
> +                        <0 0 0 4 &pcie_intc 4>;
> +        ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
> +              0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;

Misaligned.


Best regards,
Krzysztof
Re: [PATCH] dt-bindings: pci: altera: covert to yaml
Posted by matthew.gerlach@linux.intel.com 1 year, 10 months ago 

On Fri, 29 Mar 2024, Krzysztof Kozlowski wrote:

> On 29/03/2024 18:00, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Covert the device tree bindings for the Altera Root
>> Port controller from text to yaml.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>
> ...
>
>> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> new file mode 100644
>> index 000000000000..8f1ad1362ad1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> @@ -0,0 +1,106 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2024, Intel Corporation
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera PCIe Root Port
>> +
>> +maintainers:
>> +  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> +
>> +allOf:
>> +  - $ref: /schemas/pci/pci-bus.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +          - altr,pcie-root-port-1.0
>> +          - altr,pcie-root-port-2.0
>> +
>> +  reg:
>> +    minItems: 2
>> +    maxItems: 3
>> +
>> +  reg-names:
>> +    description:
>> +      TX slave port region (Txs)
>> +      Control register access region (Cra)
>> +      Hard IP region if altr,pcie-root-port-2.0 (Hip)
>
> All these go to reg as description of items.
>
> Both - reg and reg-names - need constraints per variant in
> allOf:if:then:. Move allOf: to bottom of file, just like example-schema
> is showing.

I understand. I added a constraint and moved allOf: to bottom of file, 
just like the example-schema is showing.

>
>
>> +
>> +    items:
>> +      - const: Txs
>> +      - const: Cra
>> +      - const: Hip
>> +    minItems: 2
>> +
>> +  device_type:
>> +    const: pci
>
> I don't think you need it.

I removed it.

>
>> +
>> +  "#address-cells":
>> +    const: 3
>
> Drop

Dropped

>
>> +
>> +  "#size-cells":
>> +    const: 2
>
> Drop

Dropped

>
>> +
>> +  interrupts:
>> +    minItems: 1
>
> This should be maxItems.

I changed it to maxItems

>
>> +
>> +  interrupt-map-mask:
>> +    items:
>> +      - const: 0
>> +      - const: 0
>> +      - const: 0
>> +      - const: 7
>
> I guess as well.
>
>> +
>> +  interrupt-map:
>> +    maxItems: 4
>> +
>> +  "#interrupt-cells":
>> +    const: 1
>
> Drop

If I remove "#interrupt-cells", then I get the following error:
/home/mgerlach/git/linux-next/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml: 
properties: '#interrupt-cells' is a dependency of 'interrupt-map'
 	from schema $id: 
http://devicetree.org/meta-schemas/interrupts.yaml#

>
>> +
>> +  msi-parent:
>> +    description: Link to the hardware entity that serves as the MSI controller.
>
> Just true.
>
> Please open existing, recent PCI bindings and look how it is done.

I see a couple of examples of the following:

   msi-parent: true


>
>> +
>> +  bus-range:
>> +    description: PCI bus numbers covered.
>
> Drop

Dropped.

>
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - device_type
>> +  - "#address-cells"
>> +  - "#size-cells"
>> +  - interrupts
>> +  - interrupt-map
>> +  - interrupt-map-mask
>> +  - "#interrupt-cells"
>
> This also needs cleaning.

I removed Dropped items.

>
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    pcie_0: pcie@c00000000 {
>> +        compatible = "altr,pcie-root-port-1.0";
>> +        reg = <0xc0000000 0x20000000>,
>> +            <0xff220000 0x00004000>;
>
> Misaligned.

I fixed the alignments.

>
>> +        reg-names = "Txs", "Cra";
>> +        interrupt-parent = <&hps_0_arm_gic_0>;
>> +        interrupts = <0 40 4>;
>
> Use defines for common constnats.

I added constants from arm_gic.h and irq.h.

>
>> +        #interrupt-cells = <1>;
>> +        bus-range = <0x0 0xFF>;
>
> Lowercase hex

I changed to lower case.

>
>> +        device_type = "pci";
>> +        msi-parent = <&msi_to_gic_gen_0>;
>> +        #address-cells = <3>;
>> +        #size-cells = <2>;
>> +        interrupt-map-mask = <0 0 0 7>;
>> +        interrupt-map = <0 0 0 1 &pcie_intc 1>,
>> +                        <0 0 0 2 &pcie_intc 2>,
>> +                        <0 0 0 3 &pcie_intc 3>,
>> +                        <0 0 0 4 &pcie_intc 4>;
>> +        ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
>> +              0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
>
> Misaligned.
>
>
> Best regards,
> Krzysztof
>
>

Thank you for the timely and thorough review. Version 2 of the patch will 
be submitted soon.

Matthew Gerlach

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.