StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
conventional CMO method. This driver provides the cache handling on StarFive
RISC-V SoC.

Joshua Yeong (4):
  riscv: asm: vendorid_list: Add StarFive Technology to vendors list
  riscv: errata: Add StarFive alternative ports
  cache: Add StarLink-500 cache management for StarFive  JH8100 RISC-V
    core
  dt-bindings: cache: Add docs for StarFive StarLink-500 cache
    controller

 .../cache/starfive,starlink-500-cache.yaml    |  62 ++++++++
 arch/riscv/Kconfig.errata                     |  21 +++
 arch/riscv/errata/Makefile                    |   1 +
 arch/riscv/errata/starfive/Makefile           |   1 +
 arch/riscv/errata/starfive/errata.c           |  95 ++++++++++++
 arch/riscv/include/asm/alternative.h          |   3 +
 arch/riscv/include/asm/errata_list.h          |   5 +
 arch/riscv/include/asm/vendorid_list.h        |   1 +
 arch/riscv/kernel/alternative.c               |   5 +
 drivers/cache/Kconfig                         |   9 ++
 drivers/cache/Makefile                        |   1 +
 drivers/cache/starlink500_cache.c             | 137 ++++++++++++++++++
 12 files changed, 341 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
 create mode 100644 arch/riscv/errata/starfive/Makefile
 create mode 100644 arch/riscv/errata/starfive/errata.c
 create mode 100644 drivers/cache/starlink500_cache.c

--
2.25.1

On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> conventional CMO method. This driver provides the cache handling on StarFive
> RISC-V SoC.

Unlike the other "non-conventional" CMO methods, the jh8100 does not
pre-date the Zicbom extension. Why has that not been implemented?
How many peripherals on the jh8100 rely on non-coherent DMA?

Cheers,
Conor.

On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> > conventional CMO method. This driver provides the cache handling on StarFive
> > RISC-V SoC.
> 
> Unlike the other "non-conventional" CMO methods, the jh8100 does not
> pre-date the Zicbom extension. Why has that not been implemented?

Stefan pointed out on IRC yesterday that one of the main selling points
is the ease of operating on large ranges.

> How many peripherals on the jh8100 rely on non-coherent DMA?
> 
> Cheers,
> Conor.